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| [ASAHI KASEI] [AK7750] AK7750 Audio DSP with Built-in Hands-Free Phone Features General Description The AK7750 is a highly integrated Audio Digital Signal Processor with a stereo audio codec in one chip. The AK7750 combines an on-chip DSP and an ARM7 processor that can be used to create Echo Cancellation (EC) and Noise Cancellation (NC) functions. These functions make the AK7750 a perfect choice for hands-free phones that require suppressing acoustic echo and noise. Voice quality and noise suppression levels can be precisely adjusted by externally setting various parameters. Additionally, no external Flash, ROM, or RAM is required as memories for Echo and Noise Cancellation are integrated onchip. By using an external microprocessor to change algorithms, the AK7750 can be used in other audio applications including sound field enhancements like surround, volume control, parametric equalizer and speaker compensation. These functions are simplified by the AK7750 through the integration of 64K bit delay data RAM, a high-performance audio Codec with sample rates from 8 KHz ~ 48 KHz, and 8channels of Digital Audio input / output. What's more, the latest Surround Decoders can be also be implemented by using the certified algorithms from various technology partners. Features [DSP Block] Data Word Length: 24 bit Machine Cycle: 27.1 ns (fastest) (768fs at 48 KHz) Number of Steps: 768 steps max. at fs = 48 KHz 4608 steps max. at fs = 8 KHz 192 steps max. at fs = 192 KHz Multiply: 24 x 16 -> 40 bit (enables double precision operation) Division: 24 / 24 -> 24 bit or 16 bit ALU: 34 bit arithmetic operation (overflow margin 4 bits) 24 bit arithmetic & logic operations Shift: 1,2,3,4,6,8,15 Bit Left Shift with indirect shift function 1,2,3,4,8,14,15 bit Right Shift with indirect shift function Program RAM (PRAM): 768 words x 32 bit Coefficient RAM (CRAM): 1024 words x 16 bit Data RAM (DRAM): 256 words x 24 bit Offset RAM (OFRAM): 48 words x 12 bit Delay RAM (DLRAM): 64K bits (following 3 types are selectable): - 1K words 24 bit - 1K words 24 bit & 2K words 16 bit (limited pointer capability) - 4kword 16bit Data Compression/Expansion circuits for 16 bit data handling are integrated on-chip (Dynamic-range: 23 bit equivalent, S/N+D: 15 bit equivalent (FS)). - In Hands-free mode, Delay RAM cannot be used. Registers: 34 bits x 4 (ACC) [for ALU] 24 bit x 8 (TMP) [for DBUS Interface] 24 bit x 6 stage stacks (PTMP) [for DBUS Interface] On-chip ARM7TDMI Processor: [MS0296-E-00] 1 2005/03 [ASAHI KASEI] [AK7750] [ADC Block] 24 Bit 2 Channels (fs: 8 KHz ~ 48 KHz) S/N+D: 91 dB (fs = 48 KHz) Dynamic Range & S/N: 98 dBA (fs = 48 KHz) On-chip DC offset canceling High Pass Filter [DAC Block] 24 Bit 2 Channels S/N+D: 86 dB (fs = 48 KHz) Dynamic Range & S/N: 98 dBA (fs = 48 KHz) [Input/Output Digital Interface] Serial Data Input 8 channels (10 channels with on-board codec.) Serial Data Output 6 channels (8 channels with on-board codec.) Microprocessor Interface: 1 set of inputs and outputs [General] On-chip PLL On-chip EEPROM (AK6512C, AK6514C) Interface Single 3.3 V +/- 0.3 V Power Supply Operating Temperature Range: -40C to +85C 64-Pin LQFP [MS0296-E-00] 2 2005/03 [ASAHI KASEI] [AK7750] Block Diagram (1) Hands-Free Mode Diagram DSP Block Speaker D/A Echo Canceller VAD Filter A/D Tel. Line Ctrl. VAD Tel. Line D/A voice SW Filter iFFT Spectrum Subtraction FFT Filter + A/D Mic. Digital OUT(8ch) Digital IN(8ch) P I/F I/F Noise Canceller ARM Processor RAM ROM PLL EEPROM Block Diagram (2) Audio Surround Mode Diagram DSP Block Speaker D/A Sound processing (EQ,Surround,...) A/D Audio_in Speaker D/A voice SW A/D Audio_in Digital OUT(6(8))ch) Digital IN(8(10))ch) P I/F I/F ROM RAM iFFT VAD Spectrum Subtraction FFT PLL Noise Canceller ARM Processor OFF EEPROM Block Diagram [MS0296-E-00] 3 2005/03 [ASAHI KASEI] [AK7750] (2) Total Block Diagram 1) EESEL = " L " AINR+ AINRVREFL VCOM VREFH AOUTL AOUTR pull down Hi-z @ CS ="H" ADC SDATA_AD SWIA REF DAC AVDD AVSS BVSS DVDD ctrl reg sw SDATA_DA SWQD JX0/SDIN5A SDIN4/JX1 HF SDIN3/JX2 SDIN2 SDIN1 SWJX0_N JX0 SWJX1 SWJX2 JX1 JX2 SDIN5 SDIN4 SDIN3 SDIN2 SDIN1 SDOUT2 SDOUT1 SDOUT4 SDOUT3 HF OUT3E_N OUT2E_N SWQ4 OUT4E DVSS SDOUT4A SDOUT3 SDOUT2 SDOUT1 OUT1E_N RQ SCLK SI SO RDY DSP SDOUTH DRDY HFST SDINH ARM TESTI1 TESTI2 HFST HFST_N INIT_RESET CK_RESET S_RESET CS EESEL="L" CKSX CKS1 CKS0 CONTROLLER EEPIF EEST EESI EECK EECS_N EESO EEADR XTI PLL&DIVIDER XTO CLKO LRCLK_O BITCLK_O SMODE LRCLK_I BITCLK_I LFLT The above shows a simplified AK 7750 block diagram. It does not necessarily show the circuit diagram. [MS0296-E-00] 4 2005/03 [ASAHI KASEI] [AK7750] 2) EESEL = " H " AINL+ AINLAINR+ AINRVREFL VCOM VREFH AOUTL AOUTR pull down ADC ctrl reg sw SDATA_AD SWIA REF DAC SDATA_DA AVDD AVSS BVSS DVDD SWQD DVSS OUT4E SDOUT4A HF SDOUT2 SDOUT1 SDOUT3 SDOUT2 OUT2E_N SDOUT1 OUT1E_N JX0 JX0/SDIN5A SDIN4/JX1 HF SDIN3/JX2 SDIN2 SDIN1 SDIN5 SDIN4 SDIN3 SDIN2 SDIN1 SDOUT4 SDOUT3 SWQ4 OUT3E_N SWJX0_N SWJX1 SWJX2 RQ SCLK JX1 JX2 RDY SI SO DRDY HFST RDY/EESI DRDY/EECK DSP SDOUTH SDINH SWEE HFST HFST_N/EEST ARM TESTI1 TESTI2 EEST INIT_RESET CK_RESET S_RESET CONTROLLER EEPIF EESI EECK EECK_N EESO EEADR EESEL="H" CKSX="H" CKS1 CKS0 XTI PLL&DIVIDER XTO CLKO LRCLK BITCLK SMODE LFLT The above shows a simplified AK 7750 block diagram. It does not necessarily show the circuit diagram. [MS0296-E-00] 5 2005/03 [ASAHI KASEI] [AK7750] (3) DSP Block Diagram CP0,CP1 DP0,DP1 DP0,DP1 DLRAM OFRAM 1kw x 24bit or 4kw x 16bit 48w x 12bit 1kw x 24bit & 2kw x 16bit CMP(comp/decomp) CRAM 1024w x 16bit CBUS(16bit) DRAM 256w x 24bit DBUS(24bit) MPX16 MPX24 Micon I/F Control Serial I/F X Multiply Y DEC PRAM 768w x 32bit PC Stack : 1level 16bit x 24bit 40bit 40bit MUL 34bit 24bit TMP 8 x 24bit DBUS SHIFT 34bit PTMP(LIFO) 6 x 24bit 2 x 24/20/16bit 2 x 24/20/16bit 2 x 24/20/16bit 2 x 24/20/16bit 2 x 24/20/16bit SDIN5A or from ADC SDIN4 SDIN3H or from ARM SDIN2 SDIN1 SDOUT4A SDOUT3 SDOUT2 SDOUT1 or to DAC or to ARM A ALU 34bit B Overflow Margin: 4bit DR0 3 24bit Over Flow Data Generator 2 x 24bit 2 x 24bit 2 x 24bit 2 x 24bit Division 24/224or16 Peak Detector [MS0296-E-00] 6 2005/03 [ASAHI KASEI] [AK7750] Input/Output Pin Description (1) Pin Assignment Note) *** indicates Pulled-down pins ( xxx : pin name) VREFH VREFL AOUTR AOUTL VCOM AINR+ AINL+ AVDD AVDD AINR- AVSS AVDD 50 AVSS AVSS 51 AINL- 64 63 62 61 60 59 58 57 56 55 54 53 52 49 LFLT TESTI2 EESEL SDOUT4A SDOUT3 SDOUT2 SDOUT1 DVDD DVSS BVSS DVSS DVDD CLKO BITCLK_O/BITCLK LRCLK_O/ EECS BITCLK_I/EEADR LRCLK_I/LRCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 TESTI1 CKS0 CKS1 BVSS DVSS DVDD CKSX SMODE SCLK SI SO RQ DVDD DVSS XTI XTO 64pin LQFP (TOP VIEW) 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CS /EESO 31 INIT_RESET CK_RESET S_RESET DRDY/EECK *** pins (*** is pin name) are pulled down to the digital ground of the device INTERNALLY. The words, "pulled-down" with italic type characters in the following "Pin Functional Description" are used to clarify this function. [MS0296-E-00] 7 HFST /EEST RDY/EESI DVSS DVDD SDIN2 SDIN4/JX1 JX0/SDIN5A SDIN3/JX2 SDIN1 DVDD DVSS 32 2005/03 [ASAHI KASEI] [AK7750] (3) Pin Functional Description Pin NO. 1 2 Pin Name TESTI2 EESEL I/O Function Pin Classification 3 4 5 6 7 8 9 10 11 12 13 14 I Test pin (pulled-down). Connect to DVSS Test Control I Control mode select pin (pulled-down) EESEL="L": for general use EESEL="H": program can be downloaded to the AKM's EEPROMs, AK6512C, AK6514C. EESEL pin must be fixed to either "L" or "H" level. SDOUT4A O DSP Serial Data Output pin Digital - MSB-justified 24 Bit data is output. Serial data output - ADC Data output, selected by Control Register setting. SDOUT3 O DSP Serial Data Output pin - MSB-justified 24 Bit data is output. - "L" is output during the hands-free operation. SDOUT2 O DSP Serial Data Output pin - MSB-justified 24 Bit data is output. SDOUT1 O DSP Serial Data Output pin - MSB-justified 24 Bit data is output. DVDD - Digital Power Supply pin 3.3 V (typ) Digital Power Supply DVSS - Digital Ground pin 0 V Digital Power Supply BVSS - Ground pin (silicon substrate potential) Analog Power Supply Connect to AVSS. DVSS - Digital Ground pin 0 V Digital Power Supply DVDD - Digital Power Supply pin 3.3 V (typ) Digital Power Supply CLKO O Clock Output pin Clock Output Set by Control Register BITCLK_O O Serial Bit Clock Output pin System Clock (EESEL="L") SMODE="H": 64fs clock is output during master mode operation. SMODE="L": BITCLK-I clock is output during slave mode operation (except for DIF mode 5 and 6) I/O Serial Bit Clock Input/Output pin BITCLK System Clock (EESEL="H") SMODE="H": 64fs clock is output during master mode operation. SMODE="L": 64fs clock is input during slave mode operation (48fs clock can be output, except when using CKSX=L) LRCLK_O O L/R Channel Select Output pin System Clock (EESEL="L") SMODE="H": 1fs clock is output during master mode operation. SMODE="L": LRCLK-I clock is output during slave mode operation (except for DIF mode 5 and 6). O EEPROM Chip Select Output pin EEP EECS Connect to CS pin of AK6512C/14C. (EESEL="H") [MS0296-E-00] 8 2005/03 [ASAHI KASEI] [AK7750] Pin Pin Name NO. 15 BITCLK_I (EESEL="L") I/O Function Pin Classification EEADR (EESEL="H") 16 LRCLK_I (EESEL="L") LRCLK (EESEL="H") 17 DRDY (EESEL="H") DRDY/EECK (EESEL="H") I Serial Bit Clock Input pin Sytem Clock SMODE="H": When master mode is used, connect this pin to DVSS. SMODE="L": 64fs clock is input during slave mode operation. (48fs clock can be input except for CKSX="L"). BITCLK-I (64fs) can be used as master clock (CKSX="L") during slave mode operation I EEP Address Select pin EEP AK6512C: used at EEADR="L". AK6514C: read data starting at 0000h when EEADR="L". Read data starting at 2000h when EEADR="H". I L/R Channel Select Input pin System Clock SMODE="H": When master mode is used, connect this pin to DVSS. SMODE="L": 1fs clock is input during slave mode operation. I/O L/R Channel Select Input/Output pin System Clock SMODE="H": 1fs clock is output during master mode operation SMODE="L": 1fs clock is input during slave mode operation O Output Data Ready pin (Hi-Z) C For microprocessor interface Hi-Z state when CS ="H". O Output Data Ready pin for C interface / EEP/C EEPROM Serial Data Output pin. Connect this pin to SCK pin of AK6512C/14C. After an EEPROM data read, (EEST transition from "L" to "H"), this pin is automatically switched to DRDY pin. External Conditional pin/DSP Serial Data Input pin (pulledDigital down). Conditional input / - For normal use, this is the external conditional jump pin Serial data input (JXO). - Input to the DSP's SDIN5 port is possible by setting a Control Register (normally SDIN5 is connected to ADC Serial Output, refer to block diagram). Supports MSBjustified 24 Bit /LSB-justified 24 Bit, 20 Bit, 16 Bit data formats. I DSP Serial Data Input pin/External Conditional pin (pulledDigital down) Serial data input - Supports MSB-justified 24Bit /LSB-justified 24Bit, 20Bit, /conditional input 16bit formats - This pin can be used as external conditional jump pin JX1 by setting a control register 18 JX0/SDIN5A 19 SDIN4/JX1 [MS0296-E-00] 9 2005/03 [ASAHI KASEI] [AK7750] Pin Pin Name NO. 20 SDIN3/JX2 I/O Function Pin Classification 21 SDIN2 22 SDIN1 23 24 25 DVSS DVDD INIT_RESET 26 CK_RESET 27 28 29 30 S_RESET DVDD DVSS CS (EESEL="L") I DSP Serial Data Input pin/External Conditional pin (pulledDigital down) Serial data input - Supports MSB-justified 24 Bit/LSB-justified 24 Bit, 20 Bit, /conditional input and 16 Bit data formats. - This pin can be used as external conditional jump pin JX2 by setting a control register. - This pin cannot be used as a Serial Data input pin nor external conditional pin during hands-free mode. I Digital DSP Serial Data Input pin (pulled-down) Serial Data Input Supports MSB-justified 24 Bit/ LSB-justified 24 Bit, 20 Bit, and 16 Bit data format. I DSP Serial Data Input pin (pulled-down) Supports MSB-justified 24 Bit/ LSB-justified 24 Bit, 20 Bit, and 16 Bit data format. - Digital Ground pin 0 V Digital Power Supply - Digital Power Supply pin 3.3 V (typ) I Initial Reset N pin (for initialization) Reset This is used to initialize the AK7750.This is also used to change CKS1 and CKS0 pin settings and to change XTI input frequency. I CK Reset N pin This pin is used while S_RESET is at "low" to change XTI input frequency and to change CKS2, CKS1, CKS0 settings. CK_RESET bit in control register has similar function. When CK_RESET bit is used, CK_RESET pin must be commonly controlled with INIT_RESET pin or it must be set to "high". I System Reset N pin - Digital Power Supply pin 3.3 V (typ) Digital Power Supply - Digital Ground pin 0 V Digital Power Supply I Chip Select pin for C interface (pulled-down) C Leave open or connect to DVSS for normal operation When CS ="H", data on SI pin is not written and SO, RDY, DRDY pins become Hi-Z state. This function is not available at EESEL="H". EEP EEPROM Serial Data Output pin (pulled-down) Connect this pin to SO pin of AK6512C / 14C. O Hands-Free Status pin C Normally at "H" but when an error occurs, it switches to "L" level. O Hands-Free Status pin / EEPROM write status pin C /EEP Normally at "H" but when an error occurs, it switches to "L". Level (SWEE bit = 0 in control register). When data read from EEPROM is complete, EEST changes from "L" to "H". The C input interface is enabled (SWEE bit = 1 in control register). I EESO (EESEL="H") 31 HFST (EESEL="L") HFST EEST (EESEL="H") [MS0296-E-00] 10 2005/03 [ASAHI KASEI] [AK7750] Pin Pin Name NO. 32 RDY (EESEL="L") RDY/EESI (EESEL="H") I/O Function Pin Classification 33 XTO 34 XTI 35 36 37 DVSS DVDD RQ 38 39 SO SI O Data Write Ready pin for C Interface (Hi-Z) C This pin becomes Hi-Z when CS ="H". EEP/C O Data Write Ready pin for uC interface/ EEPROM Serial Data Input Pin Connect this pin to SI pin of AK6512C/14C. When data read from EEPROM is complete (EEST changes from "L" to "H"), this pin is automatically switched to the RDY pin function. System Clock O Oscillator Circuit Output pin When a quartz crystal oscillator is used, it is connected between XTI pin and XTO pin. When an external clock is used, keep this pin open. I Oscillator Circuit Output pin When a quartz crystal oscillator is used, it is connected between XTI pin and XTO pin. An external clock should be fed to this pin when no quartz crystal oscillator is used. - Digital Ground pin 0 V Digital Power Supply - Digital Power Supply pin 3.3 V (typ) I Request N pin for C Interface C C interface is enabled when RQ ="L". Read operations during RUN mode should be made when RQ ="H". RQ should be kept "H" during the reset operation and when an external C is not used. O Serial Data Output pin for C interface C This pin becomes Hi-Z state at CS ="H" when EESEL is at "L". I Serial Data Input/Serial Data Output Control pin for C C interface If no data is input to this pin or it is not used as Serial Data Output Control pin, set SI at "L". I Serial Data Clock pin for C interface C If no clock is used, set SCLK at "H". Control I Slave / Master Mode Select pin SMODE="L": Slave mode SMODE="H": Master mode I Master Clock Select pin CKSX="H":XTI, CKSX="L":BITCLK_I For normal operation, CKSX is set to "H". - Digital Power Supply pin 3.3 V (typ) Digital Power Supply - Digital Ground pin 0 V - Ground pin (silicon substrate potential) Analog Power Supply Tie this pin to AVSS. 40 41 SCLK SMODE 42 CKSX 43 44 45 DVDD DVSS BVSS [MS0296-E-00] 11 2005/03 [ASAHI KASEI] [AK7750] Pin NO. 46 47 48 49 Pin Name CKS1 CKS0 TESTI1 LFLT I/O Function Pin Classification 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 AVDD AVSS AVSS AOUTR AOUTL AVDD AVDD VREFH VCOM VREFL AVSS AINRAINR+ AINLAINL+ I Master Clock Set pin (pulled-down) Control I Master Clock Set pin (pulled-down) I Test pin (pulled-down) Test Tie this pin to DVSS. - PLL RC component connect pin Analog Block A serially connected resistor (R=22k) and capacitor (C=1.5nF) pair is connected to this pin (when PLL is not used at all, tie this pin to AVSS). - Analog Power Supply pin 3.3 V ( typ ). - Analog Ground pin 0 V (silicon substrate potential) - Analog Ground pin 0 V (silicon substrate potential) O DAC R-ch Analog Output pin O DAC L-ch Analog Output pin - Analog Power Supply pin 3.3 V (typ). - Analog Power Supply pin 3.3 V (typ). I Analog Reference Voltage Input pin This pin is normally tied to AVDD. Connect Capacitors of 0.1 uF and 10 uF between this pin and VSS. O Analog Common Voltage Output pin Connect Capacitors of 0.1 uF and 10 uF between this pin and VSS. No external circuits should be connected to this pin. I Analog Reference Voltage Input pin Tie this pin to AVSS for normal operation. - Analog Ground pin 0 V (silicon substrate potential) I ADC R-ch Analog Inverted Input pin I ADC R-ch Analog Non-Inverted Input pin I ADC L-ch Analog Inverted Input pin I ADC L-ch Analog Non-Inverted Input pin Note) Digital input pins should not be kept open, except for pulled-down pins and BITCLK-I and LRCLK-I (EESEL="L") pins in master mode (pulled-down pins are kept open or connected to DVSS when they are not used). [MS0296-E-00] 12 2005/03 [ASAHI KASEI] [AK7750] Absolute maximum rating (AVSS, BVSS, DVSS = 0 V: All voltages indicated are relative to the ground.) Item Symbol Min Max Power supply voltage Analog (AVDD) -0.3 VA 4.6 Digital (DVDD) -0.3 VD 4.6 |AVSS(BVSS) - DVSS| Note1 0.3 GND Input current IIN 10 (Except for power supply pin) Analog input voltage VINA AINL+, AINL-, AINR+, AINR-, -0.3 VA+0.3 VRADH, VRADL, VRDAH, VRDAL Digital input voltage VIND -0.3 VA+0.3 Operating ambient temperature Ta -40 85 Storage temperature Tstg -65 150 Units V V V mA V V C C Note1) AVSS, BVSS, and DVSS must be same potential. WARNING: Operation at or beyond these limits may result in permanent damage of the device. Normal operations are not guaranteed under these critical conditions in principle. Recommended operating conditions (AVSS, BVSS, DVSS = 0 V: All voltages indicated are relative to the ground.) Items Min Typ Max Units Power supply voltage AVDD VA 3.0 3.3 3.6 V DVDD VD 3.0 3.3 3.6 V Reference voltage (VREF) VREFH Note 1) VREFL Note 2) VRH VRL VA 0.0 V V Note 1) VREFH normally connect with AVDD. Note 2) VREFLnormally connect with AVSS. Note: The analog input voltage and output voltage are proportional to the VREFL and VREFH voltages. *) AKM assumes no responsibility for the usage beyond the conditions in this data sheet. [MS0296-E-00] 13 2005/03 [ASAHI KASEI] [AK7750] Electric characteristics (1) Analog characteristics (Unless otherwise specified, Ta = 25C; AVDD, DVDD = 3.3V; VREF=AVDD, VREFL=AVSS, BITCLK = 64 fs; Signal frequency 1 kHz; measuring frequency = 20 Hz to 20 kHz @48kHz; ADC with all differential inputs XTI=12.288MHz; CKSX="H"; SMODE="H"); Parameter Min Typ Max Units ADC Resolution 24 Bits Section Dynamic characteristics S/(N+D) fs = 48kHz (-1dBFS) (note1) 80 91 dB Dynamic range fs = 48kHz (A filter) (note2) 90 98 dB S/N fs = 48kHz (A filter) 90 98 dB Inter-channel isolation (f =1 kHz) (note3) 90 105 dB DC accuracy Inter-channel gain mismatching 0.1 0.3 dB Analog input Vp-p Input voltage (Note 4) 1.22 1.32 1.42 Input impedance (Note 5) 95 k DAC Resolution 24 Bits section Dynamic characteristics S/(N+D) fs = 48kHz (0 dB) 78 86 dB Dynamic range fs = 48kHz(-60 dB) 90 98 dB (A filter) (Note 2) S/N fs = 48kHz (A filter) 90 98 dB 90 Inter-channel isolation (f = 1 kHz) 105 dB DC accuracy Inter-channel gain mismatching 0.2 0.5 dB Analog output Output voltage (Note 6) 1.85 2.00 2.15 Vp-p Load resistance 10 k Load capacitance 50 pF Note: 1. When using single-ended inputs, this value is not guaranteed. 2. Indicates S/(N+D) when -60 dB signal is applied. 3. Inter-channel isolation between L-ch and R-ch at -1 dB FS signal input. 4. The full scale for analog input voltage (AIN = (AIN+) - (AIN-)) can be represented by (FS = (VREFH-VREFL) x 0.4). 5. Impedance is in inverse proportion to fs. 6. Full scale output voltage at VREFH = AVDD, VREFL = AVSS [MS0296-E-00] 14 2005/03 [ASAHI KASEI] [AK7750] (2) DC characteristics (VDD=AVDD=DVDD=3.0~3.6V,Ta=-40C~85C) Parameter Symbol High level input voltage VIH Low level input voltage VIL VOH High level output voltage Iout=-100A VOL Low level output voltage Iout=100A Input leak current Note 1) Iin Input leak current(Pull down pin) Note 1) Iid Input leak current XTI pin Iix Min 80%VDD VDD-0.5 Typ Max 20%VDD 0.5 10 22 50 Units V V V V A A A Note: 1. The pull down pins and XTI are not included. 2. The pull down pins (typ. 150k) is as follows: 1, 2, 18, 19, 20, 21, 22, 30, 46, 47, and 48. Note: Regarding the input/output levels in the text, the low level will be represented as "L" or 0, and the high level as "H" or 1. In principle, "0" and "1" will be used to represent the bus functions (serial/parallel) such as registers. (3) Current consumption (AVDD=DVDD=3.0~3.6V, Ta=25C; master clock (XTI)=12.288MHz=256fs[fs=48kHz],with PLL mode; Power supply Parameter Min Typ Max Units Power supply current note 1) Normal Speed mA 40 a) AVDD 25 mA 100 b) DVDD 85 note 1) DVDD current value may change, depending on the content of DSP program executed and clock frequency. [MS0296-E-00] 15 2005/03 [ASAHI KASEI] [AK7750] (4) Digital filter characteristics Listed values are copied as reference data from the designed values and are not the guaranteed values. They are guaranteed-by-design after passing the IC tester's digital functional test.. 4-1) ADC Section : (Ta=25C; AVDD,DVDD =3.0~3.6V; fs=48kHz; HPF=off parameter Min PB 0 Pass band (0.005dB) note2) (-6dB) Stop band Pass band ripple Note 2) Stop band attenuation Note 3, 4) Group delay distortion Group delay (Ts=1/fs) SB PR SA GD GD 26.5 Note 1) Typ 24.0 Max 21.5 - 0.005 80 0 29.3 Units kHz kHz kHz kHz dB dB s Ts Note: 1. These frequencies scale with sampling frequency (fs). Not include HPF response. 2. The pass band is from DC to 21.5kHz when fs = 48kHz. 3. The stop band is from 26.5kHz to 3.0455MHz when fs = 48kHz. 4. When fs = 48kHz, the analog modulator samples analog input at 3.072MHz. The digital filter does not attenuate the input signal in the multiple bands (n x 3.072MHz 21.99kHz; n=0, 1, 2, 3...) of the sampling frequency. [MS0296-E-00] 16 2005/03 [ASAHI KASEI] [AK7750] 4-2) DAC section a) DAF bit = `0' (CONT6 D6) (Ta=25C; AVDD,DVDD =3.0~3.6V; fs=48kHz) Parameter Symbol min Digital filter PB 0 Pass band 0.08dB (-0.28dB) (Note 1) (-6.0dB) Stop band (Note 1) SB 26.5 Pass band ripple PR Stop band attenuation SA 47 Group delay (Ts=1/fs) (Note 2) GD Digital filter+SCF Amplitude characteristics 0 to 20.0kHz typ max 21.2 - Units kHz kHz kHz kHz dB dB Ts dB 21.7 24.0 0.04 15 0.5 Note: 1. The pass band and stop band frequencies are proportional to "fs" (system sampling rate), and represents PB=0.4535fs(@-0.06dB) and SB=0.546fs, respectively. 2. The digital filter's delay is calculated as the time from setting 24 Bit data into the input register until an analog signal is output. b) DAF bit = `1' (CONT6 D6) (Ta=25C; AVDD,DVDD =3.0~3.6V; fs=48kHz) Parameter Symbol min Digital filter PB 0 Pass band 0.02dB (-0.48dB) (Note 1) (-6.0dB) Stop band (Note 1) SB 27.4 Pass band ripple PR Stop band attenuation SA 59 Group delay (Ts=1/fs) (Note 2) GD Digital filter+SCF Amplitude characteristics 0 to 20.0kHz typ max 20.6 Units kHz kHz kHz kHz dB dB Ts dB 21.7 24.0 0.01 15 0.5 Note: 1. The pass band and stop band frequencies are proportional to "fs" (system sampling rate), and represents PB=0.4292fs(@-0.06dB) and SB=0.571fs, respectively. 2. The digital filter's delay is calculated as the time from setting 24 Bit data into the input register until an analog signal is output. [MS0296-E-00] 17 2005/03 [ASAHI KASEI] [AK7750] (5) Switching characteristics 1) System clock (AVDD=DVDD=3.0 to 3.6V,Ta= -40C to 85C) Parameter Symbol Maser clock(XTI) @CKSX="H" a) when a crystal oscillator is used (note 1) CKS[1:0]=0h fXTI CKS[1:0]=1h CKS[1:0]=2h b)when an external clock is used (note 1) Duty factor (18.5MHz) (>18.5MHz) CKS[1:0]=0h (PLL operation range) CKS[1:0]=1h (PLL operation range) CKS[1:0]=2h (PLL operation range) CKS[1:0]=3h (PLL is not used) Clock rise time Clock fall time LRCLK_I,LRCLK frequency note2) Slave mode: Clock rise time Slave mode: Clock fall time fXTI fXTI min typ max Units - 11.2896 12.288 16.9344 18.432 22.5792 24.576 50 50 - MHz MHz MHz fXTI fXTI fXTI fXTI tCR tCF fs tLR tLF 40 45 11.0 16.5 22.0 33.0 60 55 12.33 18.6 24.66 37.0 6 6 192 6 6 % % MHz MHz MHz MHz ns ns kHz ns ns 8 48 BITCLK_I ,BITCLK frequency fBCLK 48 64 fs (@CKSX="H") (note3) Slave mode: high level width tBCLKH 34 ns Slave mode: high level width tBCLKL 34 ns Slave mode: clock rise time tBR 6 ns Slave mode: clock fall time tBF 6 ns BITCLK_I,BITCLK frequency fBCLK 64 fs (@CKSX="L",SMODE="L") (note 4) Duty factor 40 50 60 % Slave mode: high level width tBCLKH 34 ns Slave mode: high level width tBCLKL 34 ns Slave mode: clock rise time tBR 6 ns Slave mode: clock fall time tBF 6 ns note1) CKS1=CKS[1].CKS[0]=CKS0 note2) LRCLK and sampling rate ( fs ) must be identical. note3) 48 fs is used for slave mode ( only 64 fs is available for hands-free mode ) note4) BITCLK-I or BITCLK is used as clock input. BITCLK must be precisely divided into 64 clocks in 1 fs time. [MS0296-E-00] 18 2005/03 [ASAHI KASEI] [AK7750] 2) Reset (AVDD=DVDD=3.0 to 3.6V,Ta=-40C to 85C) Parameter Symbol tRST INIT_RESET note 1) CK_RESET S_RESET tRST tRST min 400 400 400 typ max Units ns ns ns note1) At the power-on, it is OK to keep this pin to "L". "H" transition must be made after the power-on and master clock is full running. 3) Audio Interface (AVDD=DVDD=3.0 to 3.6V,Ta= Ta=-40C to 85C, CL=20pF) Parameter Symbol min Slave mode BITCLK frequency Delay time from BITCLK"" to LRCLK note1) Delay time from LRCLK to BITCLK"" note1) Delay time from LRCLK to serial data output Delay time from BITCLK to serial data output Serial data input latch hold time Serial data input latch setup time Master mode typ 64 max 64 80 80 Units fs ns ns ns ns ns ns fs % ns ns ns ns ns ns kHz fs % ns ns ns ns ns ns fs ns ns fBCLK tBLRD tLRBD tLRD tBSOD tBSIDS tBSIDH fBCLK tBLRD tLRBD tLRD tBSOD tBSIDS tBSIDH fLRCK fBCLK tBLRD tLRBD tLRD tBSOD tBSIDS tBSIDH tLCKKH tLCLKH tLCLKL 48 40 40 40 40 BITCLK frequency BITCLK duty factor Delay time from BITCLK"" to LRCLK note1) Delay time from LRCLK to BITCLK"" note1) Delay time from LRCLK to serial data output Delay time from BITCLK to serial data output Serial data input latch hold time Serial data input latch setup time PCM Interface mode (SF/LF) LRCLK frequency BITCLK frequency BITCLK duty factor Delay time from BITCLK"" to LRCLK note1) Delay time from LRCLK to BITCLK"" note1) Delay time from LRCLK to serial data output Delay time from BITCLK to serial data output Serial data input latch hold time Serial data input latch setup time LRCLK high level width (SF) LRCLK high level width (LF) LRCLK low level width (LF) 64 50 40 40 80 80 40 40 8 64 50 40 40 80 80 40 40 64 300 1200 48 Note 1) this value is specified such that LRCLK edge and rising edge of BITCLK never overlap [MS0296-E-00] 19 2005/03 [ASAHI KASEI] [AK7750] 4) Microprocessor Interface (AVDD=DVDD=3.0 to 3.6V,Ta= Ta=-40C to 85C, CL=20pF) Parameter symbol C I/F signal RQ fall time RQ rise time SCLK fall time SCLK rise time SCLK low level width SCLK high level width C AK7750 S_RESET "" to RQ "" RQ "" to S_RESET "" RQ high level width Time from RQ "" to SCLK"" Time from SCLK"" to RQ "" SI latch setup time SI latch hold time AK7750 C (DBUS output) SCLK"" to DRDY"" Time from SI "" to DRDY"" SI high level width Delay time from SCLK"" to SO output Hold time from SCLK "" to SO outout AK7750 C (RAM DATA read-out) SI latch setup time(SI="H") SI latch setup time(SI="L") SI latch hold time Delay time from SCLK "" to SO output AK7750 C (CRC result-out) Delay time from RQ "" to SO output Delay tiem from RQ "" to SO output CS (EESEL="L" or open) CS fall time CS rise time Time from S_RESET "" to CS "" Time from CS "" to S_RESET "" CS high level width Time from CS "" to RQ "" Time from RQ "" to CS "" CS "" to SO,RDY,DRDY Hi-Z release (RL=10k) CS "" to SO,RDY,DRDY Hi-Z (RL=10k) EEPROM AK7750(EESEL="H") EESO latch setup time EESO latch hold time note3) note2) note1) min typ max 8 8 8 8 Units ns ns ns ns ns ns ns ns ns ns ns ns ns tWRF tWRR tSF tSR tSCLKL tSCLKH tREW tWRE tWRQH tWSC tSCW tSIS tSIH tSDR tSIDR tSIH tSOS tSOH tRSISH tRSISL tRSIH tSOD tRSOC tFSOD tCSF tCSR tWRCS tWCSR tWCSH tWCSRQ tWRQCS 100 100 200 200 200 200 12xtMCLK 100 100 3xtMCLK 3xtMCLK 3xtMCLK 100 100 30 30 30 100 200 50 8 8 400 400 800 400 400 600 600 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns tCSHR tCSHS tEESOS 100 ns tEESOH 100 ns Note1: Excluding an external conditional jump at reset. Note2: This is a case where the remainder of serial data D( x) ,divided by the Generator Polynomial G (x) is equal to R (x). SO becomes "H". Note3: This means that data must be taken into the microprocessor 50 ns earlier than the falling edge of RQ (this applies when no read-out is made during RUN). [MS0296-E-00] 20 2005/03 [ASAHI KASEI] [AK7750] (6) Timing waveform 6-1) System clock 1/fXTI 1/fXTI XTI tXTI=1/fXTI VIH VIL tCR 1/fs 1/fs tCF LRCLK VIH VIL tLR 1/fBCLK 1/fBCLK tLF tBCLK=1/fBCLK BITCLK tBR tBF VIH VIL tBCLKH tBCLKL 6-2) Reset INIT RESET INIT_RESET S_RESET CK_RESET VIL tRST [MS0296-E-00] 21 2005/03 [ASAHI KASEI] [AK7750] 6-3) Audio Interface a) Standard/I2S Compatible Format LRCLK tBLRD BITCLK tLRD SDOUT * tBSIDS SDIN * tBSIDH 50%DVDD tBSOD 50%DVDD tLRBD 50%DVDD 50%DVDD SDIN *=SDIN1,SDIN2,SDIN3,SDIN4,SDIN5A SDOUT *=SDOUT1,SDOUT2,SDOUT3,SDOUT4 b) PCM Format tLCLK LRCLK tLCLKH tLCLKH 50%DVDD LRCLK tBLRD tLRBD 50%DVDD BITCLK tLRD tBSOD 50%DVDD SDOUT tBSIDS tBSIDH 50%DVDD SDIN SDIN =SDIN1,SDIN2,SDIN3,SDIN4,SDIN5A SDOUT=SDOUT1,SDOUT2,SDOUT3,SDOUT4A 50%DVDD [MS0296-E-00] 22 2005/03 [ASAHI KASEI] [AK7750] 6-4) C Interface C interface signal RQ VIH VIL tWRF tSF tWRR tSR SCLK tSCLKL tSCLKH VIH VIL C AK7750 tREW tWRE 50%DVDD S_RESET RQ tWRQH 50%DVDD SCLK tWSC tSCW tWSC tSCW 50%DVDD SI tSIS tSIH 50%DVDD Note: Timing is identical in RUN mode except that S_RESET becomes "H. [MS0296-E-00] 23 2005/03 [ASAHI KASEI] [AK7750] AK7750 C(DBUS output) 1) DBUS S_RESET RQ 24bit output DVDD 50%DVDD DVSS DVDD 50%DVDD DVSS 50%DVDD 50%DV DVSS tSDR SI 50%DVDD DRDY SCLK tSOH 50%DVDD 50%DVDD SO tSOS 2) DBUS under 24 Bit output ( SI is used ) DVDD 50%DVDD DVSS DVDD 50%DVDD DVSS tSIH S_RESET RQ SI 50%DVDD 50%DVDD DRDY tSIDR SCLK 50%DVDD SO tSOS 50%DVDD [MS0296-E-00] 24 2005/03 [ASAHI KASEI] [AK7750] AK7750 C(RAM DATA read-out) 50%DVDD DVSS 50%DVDD DVSS tRSIH tRSISL S_RESET RQ SI tRSISH tRSIH tRSISL 50%DVDD SCLK 50%DVDD SO 50%DVDD tSOD AK7750 C(CRC check: remainder of D (x) / G (x) ) = R (x)) RQ tRSOC SO tFSOC 50%DVDD 50%DVDD [MS0296-E-00] 25 2005/03 [ASAHI KASEI] [AK7750] CS (EESEL="L" or OPEN) tWRCS tWCSR 50%DVDD S_RESET CS tWCSH 50%DVDD RQ tWCSRQ tCSF tWRQCS tCSR 50%DVDD CS tCSHR tCSHS VIH 50%DVDD VIL SO,RDY,DRDY 90%DVDD 50%DVDD 10%DVDD DVDD Measurement Circuit RL SO,RDY,DRDY CL RL EEPROM AK7750 EECK EESO tEESOS tEESOH 50%DVDD 50%DVDD [MS0296-E-00] 26 2005/03 [ASAHI KASEI] [AK7750] Functional Description ( 1 ) Various Pin Setting 1) CKS1,CKS0 : Master Clock ( MCLK ) Set pin CKSX : Master Clock Select pin The AK7750 usually operates using a 36.864 MHz Master Clock (MCLK) (or 33.8688 MHz). When CKSX = "H", the XTI input clock is selected by the CKS1 and CKS0 pins. In addition to the normal use described above, the AK7750 can also operate using BITCLK-I or BITCLK as a master clock input during slave mode operation (SMODE = "L") by setting CKSX = "L". Since the AK7750 is running in slave mode instead of master mode, certain modes may not be available since the AK7750 modes are restricted by the incoming audio clock. Mode setting by CKSX, CKS1, CKS0 pins a ) XTI selection at CKSX = "H" XTI CKS XTI fs: sampling frequency Internal PLL use use use not use mode [1:0] XTI Fs:48kHz series fs:44.1kHzseries 0 0h MCLK/3 12.288MHz 11.2896MHz 1 1h MCLK/2 18.432MHz 16.9344MHz 2 2h MCLK*(2/3) 24.576MHz 22.5792MHz 3 3h MCLK 36.864MHz 33.8688MHz note) CKS1 = CKS[1],CKS0 = CKS[0] A crystal oscillator cannot be used in XTI mode 3. For hands-free mode, use fs = 48 KHz. Sample-rate setting is performed using the (CONT0) control register. Usually XTI modes 0 and 1 are used (XTI mode 0 is selected when CKS1 and CKS0 pins are left open). XTI mode 2 is only used when a 512 fs clock is available externally. XTI mode 3 is used when the PLL is not used. To change clock settings after power on (CKS1, CKS0 and CKSX),an initial reset ( INIT_RESET = "L", S_RESET = "L"), or during a clock reset ( CK_RESET = "L", S_RESET = "L") should be performed. Since the PLL circuit and internal clocks are controlled by CKS1, CKS0 and CKSX pins, an erroneous operation may occur if any pin setting changes occur under any conditions other than those described above (same conditions apply when changing the input for XTI). A reset can be performed using either the pin CK_RESET or the CKRST bit (CONT0:D1) in control register. When using the register RESET, the CK_RESET pin should be set to "H" or should be linked together with INIT_RESET pin. CK_RESET (pin) CKRST(reg.) CK_RESET (H:RESET) CK_RESET (pin) and CKRST(reg.) relation [MS0296-E-00] 27 2005/03 [ASAHI KASEI] [AK7750] b) BITCLK(_I ) Selection at CKSX = "L" ( SMODE = "L" ) EESEL="L" BCK CKS mode [1:0] 0 0h 1 1h 2 2h 3 3h BITCLK_I BITCLK_I MCLK/12 MCLK/6 MCLK/3 MCLK/72 (64fs) sample rate standard speed double speed 4X speed fs=8kHz fs: sampling frequency @SMODE="L" fs:48kHz series fs:44.1kHz series 3.072MHz 2.8224MHz 6.144MHz 5.6448MHz 12.288MHz 11.2896MHz 512kHz Internal PLL use use use use EESEL="H" BCK CKS BITCLK (64fs) @SMODE="L" Internal mode [1:0] BITCLK sample rate fs:48kHz series fs:44.1kHz series PLL 0 0h MCLK/12 standard speed 3.072MHz 2.8224MHz use 1 1h MCLK/6 double speed 6.144MHz 5.6448MHz use 2 2h MCLK/3 4x speed 12.288MHz 11.2896MHz use 3 3h MCLK/72 fs=8kHz 512kHz use note1) CKS1 = CKS[1],CKS0 = CKS[0] note2)BITCLK_I clock is selected at EESEL = "L" and BITCLK clock is selected at EESEL = "H". note3) Hands-free mode is available only when BCK mode 3 is selected. BCK modes are also used to generate internal master clock other than used as a primary bit clock. Therefore some limitations exist when to use BITCLK (_I) (for details, please refer to item b) of the Clock Source description). BCK mode is not available when the device operates at master mode. The sampling rate is fixed by BCK mode that is not affected by the speed setting (standard speed, double speed, and 4x speed) of the control register. Both of internal ADC and DAC are not available when BCK mode 1or 2 is selected. PSAD(D7) bit in CONT2 register and PSCODEC(D7) bit in the CONT6 register should be set to "1". Please set XTI = "L" when XTI is not used at all. When to switch setting of CKS1, CKS0 and CKSX after the power-on, it should be done either during the initial reset ( INIT_RESET = "L", S_RESET = "L" ) or during the clock reset ( CK_RESET = "L", S_RESET = "L" ). Since PLL circuit and internal clocks are controlled by CKS1, CKS0 and CKSX pins, an erroneous operation may occur if any pin set change is taken place under any conditions other than those described above (same conditions apply when to change input BITCLK(_I)). Instead of CK_RESET , D1 bit in control register (CONT0: D1 ) can be used. In this case, CK_RESET pin should be set to "H" or should be linked together with INIT_RESET pin. CK_RESET (pin) CKRST(reg.) CK_RESET (H:RESET) CK_RESET (pin) and CKRST(reg.) relation [MS0296-E-00] 28 2005/03 [ASAHI KASEI] [AK7750] Clock Sources a ) XTI selection at CKSX = "H". Clocks can be supplied to the AK7750's XTI pin as follows: When one of the XTI Modes 0,1 and 2 is used, either connect a proper crystal oscillator between XTI and XTO pins or feed a clock of proper frequency to the XTI pin. XTI XTO AK7750 When a crystal oscillator is used: XTI Modes 0,1,2 When XTI Mode 3 is used, feed a clock of proper frequency to the XTI pin. XTI External Clock XTO AK7750 When an external clock is used : XTI Mode 3 [MS0296-E-00] 29 2005/03 [ASAHI KASEI] [AK7750] b) BITCLK(_I) Selection at CKSX = "L" (SMODE="L") BCK Modes 0,1,2 are used when bit clock ( BITCLK_I,BITCLK ) is used instead of XTI. A clock fed on the BITCLK-I pin is directly frequency-multiplied by the PLL and a master clock (MCLK) is generated. XTI 0 1 Divider XTO BITCLK_I Cloc BITCLK EESEL SMODE CKSX 0 1 PLL MCLK BITCLK AK7750 Internal connection image diagram Input on BITCLK(_I) pin a divided-by-64 clock of the LRCLK(_I) ( 64fs ). ( BITCLK( _I) must be in synchronized with LRCLK (_I)). LRC LK _I LRC LK B IT C L K _ I B IT C L K L e ft c h R ig h t c h 3 2 x B IT C L K _ I(B IT C L K ) Figure 3 2 x B IT C L K _ I(B IT C L K ) BITCLK ( -I ) and LRCLK ( -I ) relation ( BITCLK ( -I ) = LRCLK ( -I ) / 64 ) [MS0296-E-00] 30 2005/03 [ASAHI KASEI] [AK7750] Modes vs. PLL Relation a) XTI Selection at CKSX = "H" In the AK7750, the internal master clock MCLK usually runs at 36.864 MHz max. as shown below. XTI mode0 XTI mode1 XTImode2 XTImode3 XTI 12.288MHz/11.2896MHz XTI 18.432MHz/16.9344MHZ Divider & PLL XTI 24.576MHz/22.5792MHz MCLK 36.864MHz/33.8688MHz XTI 36.864MHz/33.8688MHz MCLK 36.864MHz/33.8688MHz Figure Mode Set vs. MCLK (internal master clock) relation b) BITCLK( _I) Selection at CKSX = "L" ( @SMODE = "L" ) In the AK7750, the internal master clock MCLK usually runs at 38.864 MHz max. as shown below. BCK mode0 BCK mode1 BCK mode2 BITCLK I 3.072MHz/2.8224MHz (fs=48kHz/44.1kHz only) BITCLK I 6.144MHz/5.6448MHz (fs=96kHz/88.2kHz only) Divider & PLL BITCLK I 12.288MHz/11.2896MHz MCLK (fs=192kHz/172.4kHz only) 36.864MHz/33.8688MHz Figure Mode Set vs. MCLK ( internal master clock ) relation [MS0296-E-00] 31 2005/03 [ASAHI KASEI] [AK7750] 2) SMODE: Slave, Master Mode Select pin Set the input /output of LRCLK and BITCLK. a) Slave Mode : SMODE = "L " * EESEL = " L " LRCLK_I (1fs) & BITCLK_I (64fs) become inputs. LRCLK_I,BITCLK_I are directly output on LRCLK_O and BITCLK_O respectively. Output can be set via a control register. Note) 48fs can be input on BITCLK_I pin for modes other than hands-free mode or when CKSX = "L" (64fs corresponds to hands-free mode and CKSX = "L"). CD etc (Master Equip.) LRCLK_I BITCLK_I SMODE LRCLK_O BITCLK_O DAC etc. (Slave Equip.) CLKO AK7750 XTI Clk Gen. At CKSX = "H", XTI and LRCLK_I must be synchronized, but need not be in phase. At CKSX = "L", BITCLK_I and LRCLK_I must be synchronized. * EESEL = "H" LRCLK (1fs) and BITCLK (64fs) become inputs. At CKSX = "H", XTI and LRCLK must be synchronized, but need not be in phase. At CKSX = "L", BITCLK and LRCLK must be synchronized. Note) 48fs can be input on BITCLK pin except in hands-free mode (64fs corresponds to hands-free mode). [MS0296-E-00] 32 2005/03 [ASAHI KASEI] [AK7750] b) Master Mode: SMODE = "H" Master mode requires a clock input to XTI. When a clock is applied to the XTI input, LRCLK (LRCLK_O) and BITCLK (BITCLK_O) are automatically generated by an XTI-synchronized internal counter. No output is available on LRCLK (LRCLK_O) and BITCLK (BITCLK_O) pins during an initial reset ( INIT_RESET = "L" ) or a system reset ( INIT_RESET = "H" and S_RESET = "L" ). * EESEL = "L" LRCLK_O(1fs ) and BITCLK_O( 64fs ) are output. When LRCLK_I and BITCLK_I pins are not connected to any external circuit, these pins should be tied low ( "L" level, (DVSS)). When the AK7750 is used in Analog-to-Analog fashion and when LRCLK_O and BITCLK_O are not required (SDIN and SDOUT pins are not used), BITCLK_O and LRCLK_O can be programmed by setting a control register. * EESEL = "H" LRCLK ( 1fs ) and BITCLK ( 64fs ) are output. When the AK7750 is used in Analog-to-Analog fashion and when LRCLK and BITCLK are not required (SDIN and SDOUT pins are not used), BITCLK_O and LRCLK_O can be programmed by setting a control register. c) SMODE Pin Switching Setting the SMODE pin function after power-on should be performed either during an initial reset ( INIT_RESET = "L" and S_RESET = "L"), or during a clock reset ( CK_RESET = "L" and S_RESET = "L" ). Since switching between Slave and Master modes is controlled by the SMODE pin, an erroneous operation may occur if pin set changes take place under any conditions other than those described above. In Slave mode operation, internal clock phase-synchronization is performed at the release of system reset (from S_RESET = "L" to "H" ). It should be noted that switching to Slave mode in the middle of an operation may cause an erroneous results. d) Corresponding Table of SMODE, CKSX and EESEL pins CKSX "H" "H" "H" "H" "L" "L" "L" "L" SMODE "L" "H" "L" "H" "L" "L" "H" "H" EESEL "L" "L" "H" "H" "L" "H" "L" "H" selected CLK XTI XTI XTI XTI BITCLK_I BITCLK N/A N/A note not available not available [MS0296-E-00] 33 2005/03 [ASAHI KASEI] [AK7750] ( 2 ) Control Register Settings In the AK7750, control registers are programmed via the microprocessor interface. There are 8 registers in total. Each register is configured with 7 bits, but SCLK always requires 16 bit data clocks (8 bits for Command Code and 8 bits for DATA ). The Register configuration is listed below. Each control register value is set when D0 is written. Control register writes are performed during a system reset ( S_RESET = "L" ), but reads can be performed at any time during normal chip operation. Control registers are initialized by an INIT_RESET = "L". They are not initialized by a system reset ( S_RESET = "L" ). TEST: for testing purpose (set to "0" ) X: The value "0" must be set with a write operation. Failure to do say will result in an unknown value during a read operation. Command Code W 60h 62h 64h 66h 68h 6Ah 6Ch R 70h 72h 74h 76h 78h 7Ah 7Ch DCh CONT0 CONT1 CONT2 CONT3 CONT4 CONT5 CONT6 CONT7 DFS2 DATARAM PSAD SWJX2 TEST HF_RST_N PSCODEC SRRQ DFS1] RM OUT3E_N SWJX1 CLKS1 HF DAF CRCL DFS0 BANK1 OUT2E_N SWJX0_N CLKS0 PID SF1 TEST DIF2 BANK0 OUT1E_N SWQ4 CLKE_N SSDIN4 SF0 TEST DIF1 CMP_N NRDY SWIA BLCKE_N SSDIN3 SMUTE TEST DIF0 SS1 TEST SWQD OUT4E OP1 TEST TEST CKRST SS0 TEST SWEE TEST OP0 TEST (PLLSTBY) TEST X 0000_000x X X X X X X X 0000_000x 0000_000x 0000_000x 0000_000x 0000_000x 0000_000x 0000_000x Name D7 D6 D5 D4 D3 D2 D1 D0 Default Note) Do not write other data values or addresses. 1. In order to prevent erroneous operation, write to the CONT0 and CONT5 registers only during a system reset ( S_RESET = "L"). 2. It is recommended that CONT1 ~ CONT4, CONT6 ~ CONT7 registers are also only written to at a system reset ( S_RESET ="L"). 3. TEST means for testing, and 0 should be written. 4. Default means an initialized value, to which register is initialized by INIT_RESET = "L". [MS0296-E-00] 34 2005/03 [ASAHI KASEI] [AK7750] 1) CONT0 : Sampling Rate Selection and Interface Types writing is possible only at a system reset ( S_RESET = "L"). Command Code Write 60h Read 70h CONT0 DFS2 DFS1 DFS0 DIF2 DIF1 DIF0 CKRST X 0000_000x Name D7 D6 D5 D4 D3 D2 D1 D0 Default D7, D6, D5: DFS [2:0] DFS mode 0 1 2 3 4 DFS [2:0] 0h 1h 2h 3h 7h Sampling Rate Set DSP STEP 768 384 192 1152 4608 fs: sampling frequency AD DA operation operation fs(kHz) 48(,44.1) 96(,88.2) 192(,176.4) 32(,29.4) 8 x x x x note1) mode and sampling rate selection are only valid in modes 0 ~ 4. note2) when selecting modes 1 or 2, "1" must be set at PSAD (D7) bit of CONT2 register and at PSCODEC (D7) bit of CONT6 register. When CKSK is set to "L", operation follows the CSK0 and CSK1 setting. D4, D3, D2: DIF [2:0] DIF mode 0 1 2 3 4 Input Mode Selection of SDIN1, SDIN2, SDIN3H, SDIN4, SDIN5A DIF[2] 0 0 0 0 1 1 1 DIF[1] 0 0 1 1 0 0 1 DIF[0] 0 1 0 1 0 1 0 MSB-justified format(24bit) LSB-justified format(24bit LSB-justified format(20bit) LSB-justified format(16bit) I2S format(24bit) PCM1 SF(64fs only) PCM2 LF(64fs only) SMODE "L","H" "L","H" "L","H" "L","H" "L","H" "L" "L" D1:CKRST 0: operating condition 1: internal clock reset When CKS2, CKS1, CKS0 and SMODE pins are switched or when the XTI input clock is changed, the new settings will take effect after toggling the CKRST from "1" to "0" (similar to CK_RESET pin). D1: Set "0" note) under-lined values in ~ above indicate the default values [MS0296-E-00] 35 2005/03 [ASAHI KASEI] [AK7750] 2) CONT1: RAM control This register should be changed only during a system reset ( S_RESET ="L"). Command Code Write 62h Read 72h CONT1 DATARAM RM BANK1 BANK0 CMP_N SS1 SS0 X 0000_000x Name D7 D6 D5 D4 D3 D2 D1 D0 Default D7:DATARAM DATARAM addressing mode selector 0: Ring addressing mode 1: Linear addressing mode DATARAM is 256-words x 24-bits and has 2 addressing pointers (DP0, DP1). Ring addressing mode: The starting address increments by 1 every sample period. Linear addressing mode: The starting address is always the same, DP0 = 00h and DP1 = 80h. D6:RM: Decompress bit mode 0: SIGN bit 1: Random data When either Data Compression or Data Expansion mode is selected (CMP-N (D3) = "0"), data for the lower bits where no data exists at the data expansion is selectable. When it is "0", the sign bit is filled in and when it is "0", the M-series random number is filled in. D5,D4:BANK[1:0] DLRAM Setting Mode BANK1 BANK0 Memory 0 0 0 24bit 1kword(RAM A) 1 0 1 16bit 2kword(RAM A),24bit 1kword(RAM B) 2 1 0 24bit 1kword(RAM A),16bit 2kword(RAM B) 3 1 1 16bit 4kword(RAM A) note) When a hands-free function is used, set the DLRAM at mode0, which allocates the memory for hands-free processing. At DLRAM mode3, both Pointers 0 & 1 can be used. With DLRAM modes0, 1 and 2, Pointer 0 is allocated to RAM A and Pointer 1 is allocated to RAM B. D3:CMP_N 16bitDLRAM Compress & Decompress selector When mode 1,2 or 3 is selected, this register can turn ON or OFF the compress/decompress function. 0 : Compression / Expansion ON 1 : Compression / Expansion OFF When both compression and expansion are enabled (ON), the upper 23 bit data on DBUS is compressed to 15 bit data and it is written into DLRAM. In read mode, the 15 bit data is expanded and the resulting data is output on DBUS. Lower bit setting during data expansion follows as is set by D6 : RM. With this data compression, 23 bit equivalent Dynamic Range and 15 bit equivalent S/N + D are obtained. When both compression and expansion are disabled (OFF), the upper 16 bit data on DBUS is directly written into or read out of DLRAM. During the read operation, the lower 16 bit returns to DBUS a value of 0000h. D2,D1:SS[1:0] DLRAM setting of sampling timing (only for RAM A) Mode SS1 SS0 RAM A mode selected by BANK[1:0] 0 0 0 Update every sampling time 1 0 1 Update every 2 sampling time 2 1 0 Update every 4 sampling time 3 1 1 Update every 8 sampling time Note) When modes 1,2 or 3 are selected, aliasing will occur. D0: set to "0" Note) Underlines "_" mean default setting. [MS0296-E-00] 36 2005/03 [ASAHI KASEI] [AK7750] 3) CONT2: ADC control, Serial output set and others Change this register only during a system reset state ( S_RESET ="L"). Command Code Write 64h Read 74h CONT2 PSAD OUT3E_N OUT2E_N OUT1E_N TEST TEST TEST X 0000_000x Name D7 D6 D5 D4 D3 D2 D1 D0 Default D7:PSAD 0:Normal operation 1:ADC power save When the ADC is not used, it is put into power-save mode by setting D7 = 1 (SDATA digital output of ADC becomes 00 0000h). In a double or 4X speed mode, set this bit to "1". When returning to normal mode, write "0" to this bit during a system reset. D6: OUT3E_N 0 : SDOUT3 output enable 1 : SDOUT3 = "L" D5: OUT2E_N 0 : SDOUT2 output enable 1 : SDOUT2 = "L" D4: OUT2E_N 0 : SDOUT1 output enable 1 : SDOUT1 = "L" D3:TEST 0:Normal operation 1:Test mode (Do NOT use this mode) D2:TEST 0:Normal operation 1:Test mode (Do NOT use this mode) D1:TEST 0:Normal operation 1:Test mode (Do NOT use this mode) D0: set "0" Note): Underlines "_" mean default setting. [MS0296-E-00] 37 2005/03 [ASAHI KASEI] [AK7750] 4) CONT3 : Internal Path Select ( refer to (2) Total Block Diagram ) Writing during the system reset ( S_RESET = "L" ) is recommended. Command Code Write 66h Read 76h CONT3 SWJX2 SWJX1 SWJX0_N SWQ4 SWIA SWQD SWEE X 0000_000x Name D7 D6 D5 D4 D3 D2 D1 D0 Default D7:SWJX2 0: SDIN3 / JX2 pin is used as SDIN3 pin (JX2 = 0). 1: SDIN3 / JX2 pin is used as JX2 pin. D6:SWJX1 0: SDIN4 / JX1 pin is used as SDIN4 pin (JX1 = 0). 1: SDIN4 / JX1 pin is used as JX1 pin. D5:SWJX0_N 0: JX0 / SDIN5A pin is used as JX0 pin. 1: JX0 / SDIN5A pin is used as SDIN5A pin (JX0 =0). D4:SWQ4 0: DSP SDOUT4 is selected. 1: ADC SDATA-AD is selected. D3:SWIA 0: ADC SDATA-AD is selected. 1: JX0 / SDIN5A pin is selected. D2:SWQD 0: DSP SDOUT4 is output 1: Data selected by SWIA is output. D1:SWEE Status Information Select ( EESEL = "H" ) 0: HFST N is selected. 1: EEST is selected. D0 : set "0" note) Under-lined set values in ~ above indicate the default values. [MS0296-E-00] 38 2005/03 [ASAHI KASEI] [AK7750] 5) CONT4 : CLKO and Other Setting Writing during the system reset ( S_RESET = "L") is recommended. Command Code Write 68h Read 78h CONT4 TEST CLKS1 CLKS0 CLKE_N BLCKE_N OUT4E TEST X 0000_000x Name D7 D6 D5 D4 D3 D2 D1 D0 Default D7:TEST 0: normal operation 1: Test mode (do not use) D6,D5:CLKS1,CLKS0 CLKO Output Clock Select CLKO outputs "L" level during the system reset. After the release of the system reset, selected value is output by CLKS1 and CLKS0. CLKS mode CLKS1 CLKS0 CLKO 0 0 0 see the following table 1 0 1 MCLK/3 2 1 0 MCLK/2 3 1 1 N/A 1) in CLKS mode 0, at CKSX = "1" or ( CKSX = "L" & SMODE = "H" ) fs: sampling frequency DFS DFS fs(kHz) CLKO output mode [2:0] 0 0h 48(,44.1) 256fs 1 1h 96(,88.2) N/A 2 2h 192(,176.4) N/A 3 3h 32(,29.4) 256fs 4 7h 8 1024fs 2) in CLKS mode 0,at CKSX = "L" & SMODE = "L" fs: sampling frequency BCK CKS pin fs(kHz) CLKO mode [1:0] output 0 0h 48(,44.1) 256fs 1 1h 96(,88.2) N/A 2 2h 192(,176.4) N/A 3 3h 8 1024fs D4:CLKE_N CLKO Output Control pin 0: CLKO output select 1: CLKO output is set to "L". D3:BITCLKE_N BITCLK, LRCLK Output Control pin 0: enables outputs of BITCLK,LRCLK(@EESEL="H",SMODE="H"),BITCLK_O,LRCLK_O 1: sets BITCLK, LRCLK(@EESEL = "H", SMODE = "H" ),BITCLK_O,LRCLK_O outputs to either "L" or "H" . D2:OUT4E 0: SDOUT4A = "L" 1: SDOUT4A output enable D1:TEST 0: normal operation 1: Test mode (do not use) D0 : set "0". note) Under-lined set values in ~ above indicate the default values. [MS0296-E-00] 39 2005/03 [ASAHI KASEI] [AK7750] 6) CONT5 : HF Set & Instruction Set The setting is enabled only during the system reset ( S_RESET = "L" ). Command Code Write 6Ah Read 7Ah CONT5 HF_RST_N HF PID SSDIN4 SSDIN3 OP1 OP0 X 0000_000x Name D7 D6 D5 D4 D3 D2 D1 D0 Default D7: HF_RST_N 0: reset the ARM for hands-free use. 1: release the reset of the ARM for HF use. Set HF-RST-N = 1 and after the system reset is released, it is put into hands-free mode. In order to return from the hands-free mode to normal DSP mode, set HF-RST-N = 0. D6: HF 0: normal mode set 1: hands-free mode set DSP_SDIN3 and DSP_SDOUT3 are switched to the ARM interface. SDIN3 cannot be used (can be used as JX1). Output of PIN-SDOUT3 becomes "L". D5: PID Selection of hands-free parameters sets 0 : ROM data is used (Default set of hands-free parameters) 1 : Param Register RAM is used Noise canceller uses the customized parameter set which is allocated in RAM area. procedure for getting the optimized hands-free parameters is described in the page The [MS0296-E-00] 40 2005/03 [ASAHI KASEI] [AK7750] 7) CONT6 : DAC Setting etc Command Code Write 6Ch Read 7Ch CONT6 PS CODEC DAF SF1 SF0 SMUTE TEST TEST X 0000_000x Name D7 D6 D5 D4 D3 D2 D1 D0 Default D7:PSCODEC ADC, DAC power-down 0: normal operation 1: power -down ADC, and DAC Note1) PDAD bit in the CONT2 register must be set to "1" when this bit is set to "1". Note 2) In a double or 4X speed mode, this bit, and PSAD bit must be set to "1". D6: DAF Selection of DAC digital filter 0: DAC digital filter characteristics a) in page 17 1: DAC digital filter characteristics b) in page 17 The change must be set at system reset. When the sample rate is set to 8kHz, DAF="1" is recommended D5, D4: SF1, SF0 SF mode 0 1 2 3 Selection of DAC soft mute cycle time SF1 0 0 1 1 SF0 0 1 0 1 1008 LRCLK cycle 4032 LRCLK cycle 504 LRCLK cycle 2016 LRCLK cycle D3: SMUTE Soft Mute Selection 0 : normal operation 1 : DAC soft mute enable D2:TEST(SEL_MCLK) 0 : normal operation 1 : Test mode (do not use). D1:TEST(PLLSTBY) 0 : normal operation 1 : Test mode (do not use). D0 : set "0". note) Under-lined set values in ~ above indicate the default values. [MS0296-E-00] 41 2005/03 [ASAHI KASEI] [AK7750] 8) CONT7 : Hands-Free Status / Request Command Code Write X Read DCh CONT7 SRRQ TEST TEST TEST TEST TEST TEST X 0000_000x Name D7 D6 D5 D4 D3 D2 D1 D0 Default *) This register, together with HFST pin, is used to inform the host microcontroller that the hands-free operation is enabled. HFST pin is usually at "H" but when an exception/interrupt occurs, this pin notifies the host(this pin becomes "L", and SRRQ goes to "1"). Upon receipt of HFST = "L", the host is expected to read and process the CONT7 register, depending on the register content. This register is cleared by setting S_RESET pin to "L", and HFST pin returns to "H". Reading should be made during S_RESET = "H" (during RUN ). D7:SRRQ 0: normal operation 1: requests that the host enable S-RESET. This bit Indicates that a hardware-related error has occurred in hands-free mode. If same error occurs again , initialize the AK7750 by issuing S_RESET = "L". D6,D5,D4,D3,D2,D1,D0:TEST_MON Monitor pin for test. [MS0296-E-00] 42 2005/03 [ASAHI KASEI] [AK7750] (3) Power-ON Sequence Power-On while holding INIT_RESET = "L" and S_RESET = "L". Control registers are initialized during INIT_RESET = "L" ( see note 1 and note 2 ). After power is applied, INIT_RESET = "H" and REF generating circuit ( Analog Reference Voltage source ) and PLL are turned on, and master clock is generated by the PLL. Communication with the AK7750 should be made after the PLL oscillation is stabilized (50ms@ XTI mode, and BCK mode 0/1/2; 175ms@BCK mode 3). An initialization by INIT_RESET is usually required only for power- on. The power should be turned on when CK_RESET pin is linked with INIT_RESET or while it is fixed to "H". Note1) to assure proper initialization, it is necessary that power is turned on and then the master clock (XTI) is supplied. Note2) when a crystal oscillator is used, INIT_RESET should be set to "H" after the oscillation is stabilized. Stabilization time of the oscillation varies depending upon types of crystal oscillators and external circuits used. Note) Do not stop the system clocks (Slave Mode: XTI, LRCLK, BITCLK and Master Mode : XTI ) except during the initial reset ( INIT_RESET = "L" and S_RESET = "L" ) or at a system reset ( S_RESET = "L" ) or at a Clock reset ( CK_RESET = "L" ). If these clocks are not applied, there is a possibility that an excess current will flow, causing erratic operation. AVDD DVDD INIT_RESET ( CK_RESET ) S_RESET XTI (internal PLLCLK) CLKO INIT_RESET ="H" after crystal startup Power Off command code PLL startup time loading of DSP program Inhibit of command (no time-constraint) 50 ms@ XTI mode 50ms@BCK mode 0/1/2 175ms@BCK mode 3 start CLKO output Figure Power-up Sequence [MS0296-E-00] 43 2005/03 [ASAHI KASEI] [AK7750] (4) About Reset The AK7750 has 3 reset pins, INIT_RESET , S_RESET and CK_RESET . There are 2 reset bits in control registers HF_RESET_N (CONT5 D7) and CKRST (CONT0 D1). A clock reset CK_RESET (CKRST) will be described in section (5) , "Switching Clocks". When the CK_RESET pin is not used, either connect it to the INIT_RESET pin or set it to "H". HF_RESET_N is described in section (2) "Control Register Settings". INIT_RESET is used to initialize the AK7750 as is described in the Power-on Sequence description. When changing CKS1, CKS0, CKSX or SMODE, or when changing the XTI pin's input clock frequency, it is recommended to execute it during the initial reset ( INIT_RESET = "L", S_RESET = "L" ). A change can be made during a clock reset ( CK_RESET , CKRST) if audio interruption is acceptable and no other setting changes are made. Since the CKS1, CKS0, CKSX, SMODE and XTI pins are involved in PLL and internal clock control, erroneous operation may occur if any changes are made other than during initial reset or clock reset. With INIT_RESET = "H" & S_RESET = "L", the device is put into system reset condition (" reset "implies a system reset ). Usually program and RAM data is written during a system reset (excluding write during RUN). During a system reset, both the ADC and DAC are reset. The REF generating circuit remains in operation. CLKO output and LRCLK, BITCLK in Master mode are stopped during a system reset. System reset is released by rising S_RESET to "H", which starts the internal counters. In Master mode, LRCLK and BITCLK are generated by the AK7750's counters, which may generate a clock conflict if other devices are not properly initialized. In Slave mode, when a system reset is released, internal timing starts to operate in sync with the rising edge of LRCLK ( in standard input format ). Timing adjustment between an external clock and internal timing is made during this time. During the operation, if the phase-difference (both at the rising edge and at the falling edge) between LRCLK and internal timing is within 2 clock pulses of BITCLK (64fs), operation continues. When the phase-difference becomes larger than the above range, a phase adjustment is made in sync with the rising edge of LRCLK ( in standard input format ). This circuit protects the AK7750 from becoming out of sync with external circuits due to noise etc. Correct data is not output for a while even after out-of-sync condition returns to normal. In the ADC, data output is available 516 LRCLK clocks after the internal counters start to operate (internal counters start to operate right after the release of system reset in Master mode, or in Slave mode approximately 2 LRCLK clocks after the release of system reset). The AK7750 returns to normal operation at the rising edge of S_RESET . The AK7750 goes from normal state to system reset state by the falling edge of S_RESET . not stop the input clock for 3 MCLK times period after the falling edge of S_RESET . Please do [MS0296-E-00] 44 2005/03 [ASAHI KASEI] [AK7750] (5) About Clock Changes Changes to CKS1, CKS0, CKSX or SMODE are made during the system reset ( S_RESET = "L", INIT_RESET = "H"), or when an input clock is switched ( XTI @ CKSX= "H" or BITCLK (_I ) @ ( CKSX = "L" & SMODE = "L")). A clock reset is made using either the CK_RESET pin or by using CKRST control register bit. After a reset, the internal Master clock, MCLK, is stopped and it is safe to change settings (MCLK = 36.864 MHz or 33.8688 MHz) during the system reset. After executing a system reset, clock reset is performed by changing the CK_RESET pin from "H" to "L", and by continuously supplying a clock- for a duration of longer than 120 / MCLK [us] from the falling edge of CK_RESET ( S_RESET and CK_RESET pins can be simultaneously set to low ). When the CKRS control register is used, the duration is 120 / MCLK [us] from the rising edge of 16th clock of CONT0. Pin setting and input clock changes (XTI @ CKSX = "H" or BITCLK (_I) @ (CKSX = "L" & SMODE = "L") should be done after MCLK is stopped. After changes are made and after the input clock is stabilized to the new value, release CK_RESET from "L" to "H" and PLL is restarted. Do not transmit the DSP program and coefficient data from the microprocessor until the PLL reaches stable oscillation (about 25ms). Control register read/write operations are allowed after the input clock is stabilized to the new value. The AK7750 returns to normal operating condition by rising S_RESET to "H" after the DSP program and coefficient data are transmitted. When pin-set- and clock input switches are made and C interface is not used, it is possible to raise both the CK_RESET and S_RESET pins simultaneously to return the AK7750 to normal operation. However an internal circuit reset cannot be released until the PLL reaches its stable oscillation (about 25ms) even if S_RESET is released. S_RESET CK_RESET XTI tCKFCK pin setting clock change new input clock is stable PLLis stable (about 25ms) download DSP program read/write control register Figure CK_RESET Sequence tCKFCK CKS [1:0] 0h 1h 2h 3h table(XTI mode) tCKFCK(min) XTI cycles 40 60 80 10 fs:48kHz series 3.3s 3.3s 3. 3s 0.3s tCKFCK(min) fs:48kHz series 3.3s 3.3s 3.3s 19.5s fs:44.1kHz series 3.6s 3.6s 3.6s NA 2005/03 fs:44.1kHz series 3.6s 3.6s 3.6s 0.3s XTI mode 0 1 2 3 XTI MCLK/3 MCLK/2 MCLK*(2/3) MCLK BCK mode 0 1 2 3 [MS0296-E-00] tCKFCK table(BCK mode) CKS [1:0] 0h 1h 2h 3h BITCLK MCLK/12 MCLK/6 MCLK/3 MCLK/72 BITCLK cycles 10 20 40 10 45 [ASAHI KASEI] [AK7750] (6) Audio Data Interface Serial Audio Data pins, SDIN1, SDIN2, SDIN3, SDIN4, SDIN5A, SDOUT1, SDOUT2, SDOUT3, SDOUT4A interface with external systems using LRCLK and BITCLK. Proper control register settings are required. Please refer to the Total Block Diagram and the Control Register Setting section. Data Format is in 2's complement with MSB first. Supported Input and Output Formats are AKM's standard format plus I2S compatible mode. In this mode, interface of all input and output audio data pins are also I2S compatible. The default setting is MSB-justified 24 bit format, but by properly setting the control register CONT0 DIF1(D3), DIF0 (D2), other formats such as LSB-justified 24-bit, LSB-justified 20-bit and LSB-justified 16bit are also supported (note : CONT0 DIFS (D4) = 0 ). However, SDIN1, SDIN2, SDIN3, SDIN4 and SDIN5A must all be set to the same format, and cannot be independently set to support different formats. Outputs SDOUT1, SDOUT2, SDOUT3 and SDOUT4A are in MSB-justified, fixed-24 bit data. 1) Standard Input Format ( DIF[2] = 0 : default value ) a) DIF mode 0 ( DIF[2:0] = 0h : default value ) LRCLK BITCLK 31 30 29 28 27 Left ch Right ch 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 21L M: MSB, L: LSB M 22 21 20 19 10 9 8 7 6 5 4 3 2 1 0 21L SDIN1 5A M 22 21 20 19 When MSB-justified 20-bit data is input to SDIN1, 2, 3, 4A, fill 4 zeros ("0") in sequence, starting at the LSB of each data. b) DIF mode 1,2,3 SDIN1, 2, 3, 4, 5A SDIN1, 2, 3, 4, 5A SDIN1, 2, 3, 4, 5A mode 1: (DIF[2:0] = 1h mode 2: (DIF[2:0] = 2h mode 3: (DIF[2:0] = 3h LSB-justified 24 bit) LSB-justified 20 bit) LSB-justified 16 bit) LRCLK BITCLK 31 30 Left ch Right ch 23 22 21 20 19 18 17 16 15 14 1 0 31 30 23 22 21 20 19 18 17 16 15 14 10 1L SDIN15A DIF mode 1 SDIN15A DIF mode 2 SDIN15A DIF mode 3 [MS0296-E-00] Don't care M 22 21 20 19 18 17 16 15 14 1 L Don't care M 22 21 20 19 18 17 16 15 14 Don't care M 18 17 16 15 14 1 L Don't care M 18 17 16 15 14 1L Don't care M 14 1 L Don't care M 14 1L M: MSB, LSB: LSB 46 2005/03 [ASAHI KASEI] [AK7750] 2) I2S Compatible Input Format (DIF[2:0] = 4h) LRCLK BITCLK 31 30 29 28 27 Left ch Right ch 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 321L M: MSB, L: LSB M 22 21 20 10 9 8 7 6 5 4 3 2 1 0 321L SDIN15A M 22 21 20 3) Standard Output Format (DIF[2:0] = 0h, 1h, 2h, 3h) LRCLK BITCLK 31 30 29 28 27 Left ch Right ch 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 21L M 22 21 20 19 M: MSB, L: LSB 10 9 8 7 6 5 4 3 2 1 0 21L SDOUT1 SDOUT2 SDOUT3 SDOUT4A M 22 21 20 19 4) I2S Compatible Output Format (DIF[2:0] = 4h) LRCLK BITCLK 31 30 29 28 27 Left ch Right ch 10 9 8 7 6 5 4 3 2 1 0 31 30 29 28 27 321L M:LSB, L: LSB M 22 21 20 10 9 8 7 6 5 4 3 2 1 0 321 L SDOUT1 SDOUT2 SDOUT3 SDOUT4A M 22 21 20 [MS0296-E-00] 47 2005/03 [ASAHI KASEI] [AK7750] 5) PCM mode (DIF[2:0]=5h, 6h) i) PCM1 SF(Short Frame) mode (BITCLK(_I)=64fs : fs=8kHz 48kHz) LRCLK(_I) BITCLK(_I) FS 63 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 21L 21L M:MSB,L:LSB M 22 21 20 19 M 22 21 20 19 10 9 8 7 6 5 4 3 2 1 0 21L 21L SDIN15A SDOUT14A LRCLK_O BITCLK_O M 22 21 20 19 M 22 21 20 19 Left ch Right ch ii) PCM2 LF(Long Frame) mode (BITCLK(_I)=64fs : fs=8kHz 48kHz) LRCLK(_I) BITCLK(_I) 63 62 61 60 59 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 21L 21L M:MSB,L:LSB M 22 21 20 19 M 22 21 20 19 10 9 8 7 6 5 4 3 2 1 0 21L 21L FS SDIN15A SDOUT14A LRCLK_O BITCLK_O M 22 21 20 19 M 22 21 20 19 Left ch Right ch [MS0296-E-00] 48 2005/03 [ASAHI KASEI] [AK7750] (7) Microprocessor Interface The microprocessor interface uses 6 control signals, RQ ( ReQuest Bar ), SCLK ( Serial data input Clock ), SI ( Serial data Input ), SO ( Serial data Output ), RDY ( ReaDY ), DRDY ( Data ReaDY ). The AK7750 has 2 types of write and read operations - write / read during reset (usually refers to system reset) and, write / read during normal operation. During reset, it is possible to write data into the control registers, program RAM, coefficient RAM, offset RAM and to write external conditional jump codes. It is possible to read data from the control registers, program RAM, coefficient RAM and offset RAM. During normal operation, it is possible to write data into coefficient RAM, offset RAM, and to write external conditional jump codes. It is also possible to read data on the DBUS ( Data Bus ) via SO and to read data from control registers. Data is input or output in serial form with MSB first. The interface between the microprocessor and the AK7750 (except for DBUS read operations) is enabled by setting RQ to "L" of. Data is taken at the rising edge of SCLK and data is output at the falling edge of SCLK. As for the data format, command code is input first, then address and coefficient data is input or output. Since a single command is completed by setting RQ to "H", in order to write a new command, it is necessary to set RQ to low again after setting RQ to "H". Contrarily, DBUS data reads are of accomplished by setting RQ to "H" (no command code input ). There is a case where SI is used as control signal, depending upon the application. In this case, this pin should be protected spurious noise, as is the case of a normal clock signal.. Command Code table is listed below. Remark Command code WRITE READ CONT0 60h 70h For the function of each bit, See the description of Control CONT1 62h 72h Registers CONT2 64h 74h CONT3 66h 76h CONT4 68h 78h CONT5 6Ah 7Ah CONT6 6Ch 7Ch CONT7 DCh PRAM C0h C1h CRAM A0h A1h OFRAM 90h 91h External condition jump C4h CRC check (R(x)) B6h D6h Hands free parameter E0h E1h RUN NA above Read available, same as RESET code. CONT0CONT7 phase address CRAM rewrite preparation A8h It needs to do before CRAM rewrite CRAM rewrite A4h OFRAM rewrite preparation 98h It needs to do before OFRAM rewrite OFRAM rewrite 94h External condition jump C4h Same code as RESET CRC check (R(x)) B6h D6h Same code as RESET note: As there are some duplicated codes in use, command codes other than those listed above should not be accessed, as erroneous operation may result. If no communication exists with a microprocessor, set SCLK to "H" and SI to "L". [MS0296-E-00] 49 2005/03 Conditions for use RESET Phase Code name [ASAHI KASEI] [AK7750] 1) Write during reset phase a) Control register write (during reset phase) The data consists of 2 bytes used to perform control register write operations (during reset phase). When all data has been entered, the new data is stored in the register at the rising edge of the 16th count of SCLK. Data transfer procedure Command code Control data 60h, 62h, 64h, 68h, 6Ah, 6Ch, B8h (D7 D6 D5 D4 D3 D2 D1 D0) note) 40h, 44h and 48h are for testing and cannot be used. For the function of each bit, see the description of Control registers, (section 2). S_RESET RQ SCLK SI SO 60h D7 ***D1 D0 64h D7 ***D1 D0 Note) It must be set always 0 to D0. Control Registers write operation [MS0296-E-00] 50 2005/03 [ASAHI KASEI] [AK7750] b) Program RAM writes (during reset phase) Program RAM write operations are performed during the reset phase using 7-bytes of data. When all data has been transferred, the RDY terminal is set to "L". Upon completion of writing into the PRAM, RDY returns "H" to allow the next data bit input. When writing to sequential addresses, input the data without a command code or address. To write discontinuous data, shift the RQ terminal from "H" to "L" again and then input the command code, address and data in that order. Note) "L" period of RDY is shorter than 1 master clock (20ns) under typical condition Data transfer procedure Command code C0h (1 1 0 0 0 0 0 0) Address upper (0 0 0 0 0 0 A9 A8) Address lower (A7 . . . . . . . A0) Data (D31 . . . . . . D24) Data (D23 . . . . . . D16) Data (D15 . . . . . . D8) Data (D7 . . . . . . D0) S_RESET RQ SCLK SI RDY SO 11000000 000000A9A8 A7 ****A1A0 D31***** D0 D31***** D0 Input of continuous address data into PRAM S_RESET RQ SCLK SI RDY SO 11000000 000000A9A8 A7**A1A0 D31***D0 11000000 000000A9A8 A7**A1A0 Input of discontinuous address data into PRAM [MS0296-E-00] 51 2005/03 [ASAHI KASEI] [AK7750] c) Coefficient RAM write (during reset phase) 5 bytes of data are used to perform coefficient RAM write operations (during the reset phase). When all data has been transferred, the RDY terminal goes to "L". Upon completing the CRAM write, RDY goes to "H" to allow the next data to be input. When writing to sequential addresses, input the data as shown below. To write discontinuous data, transition the RQ terminal from "H" to "L" and then input the command code, address and data. Note) "L" period of RDY is shorter than 1 master clock (20ns) under typical condition Data transfer procedure Command code A0h Address upper Address lower Data Data S_RESET (1 0 1 0 0 0 (0 0 0 0 0 0 (A7 . . . . . (D15 . . . . (D7 .. . . 0 0) A9 A8) . . A0) . . D8) . . D0) RQ SCLK SI RDY SO 10100000 000000A9A8 A7****A1A0 D15****D0 D15****D0 Input of continuous address data into CRAM S_RESET RQ SCLK SI RDY SO 10100000 000000A9A A7***A1A0 D15****D0 8 10100000 A7***A1A0 D15** Input of discontinuous address data into CRAM [MS0296-E-00] 52 2005/03 [ASAHI KASEI] [AK7750] d) Offset RAM write (during reset phase) Offset RAM Writes (at reset) are done by writing a command code first, then address and 3 bytes/set data. After the data is transferred, the RDY pin becomes "L" and after writing Offset RAM is completed, it becomes "H" and next data can be ready to input. Data transfer procedure Command code Address Data Data Data 90h (1 (0 (0 (0 (D7 0 0 0 0 . 01 0 A5 A4 .. 000 0 0 D11 . . . 0 0 0) . . A0 ) 0 0 0) . . D8 ) . . D0 ) S_RESET RQ SCLK SI RDY SO 10010000 00A5****A0 00000000 000D12**** D8 D7****D1D0 Input of data into OFRAM [MS0296-E-00] 53 2005/03 [ASAHI KASEI] [AK7750] e) External conditional jump code write (during reset phase) External conditional jump code writes are made after all necessary operations, such as program downloads, etc. are executed. Code writes are done in 2 bytes/set data. It is possible to input during both reset and in normal operation mode. Input data is set at each assigned register at the rising edge of LCRLK. RDY pin becomes "L" . After all data is transferred and it becomes "H" when write operation is finished. External jump codes are 8-bits long and when any bit among the 11 code bits of JX0, JX1 and JX2 input pins and any single bit of "1" in the IFCON field match, the jump instruction is executed. When writing data during the reset, it can be executed only before reset is released after completing all data transfers. Setting RQ from "L" to "H" during reset mode writes should be made more than 2 MCLK clocks after reset is released. RDY becomes "H" when the next rising edge of LRCLK is detected. Write operations from the microprocessor are inhibited until RDY becomes "H". The IFCON field is an external condition, written in the DSP program. This jump code is reset to 00h by setting INIT_RESET to "L", however, it remains at its previous condition even when S_RESET ="L". Note: It should be noted that the LRCLK phase is inverted in the I2S-compatible state. 7 External condition code Check if any bit of a single "1" bit between the assigned bit by IFCON and external jump code 16 IFCON field Data transfer procedure Command code Code data S_RESET SCLK SI SO RQ LRCLK RDY 2LRCLK(max) L ch R ch 11000100 D7****D0 0 JX0 JX1 JX2 9 8 7 6 C4h ( 1 1 0 0 0 1 0 0) (D7 . . .. . D0) External conditional jump write operation timing (during reset phase) [MS0296-E-00] 54 2005/03 [ASAHI KASEI] [AK7750] f) Hands-Free Parameter RAM Write (at reset) Hands-Free Parameter RAM Write operations (at reset) are executed in 4 bytes/set data. When all data is transferred, the RDY pin becomes "L". It becomes "H" after writing into Hands-Free Parameter RAM is completed and next data can be input. When writing data at the consecutive address locations, input data as is. When writing data at the discontinuous address locations, input command code first, then address and data in this order after setting RQ-N pin from "H" to "L". Data transfer procedure Command code Address Data Data E0h ( 1 1 1 0 0 1 0 0) ( 0 0 A5 . . . . A0) (D15 . . . . . . D8) (D7 . . . . . . D0) S_RESET RQ SCLK SI RDY SO 11100000 00A5 A1 A0 D15 D0 D15 D0 Input of continuous address data into Hands-free parameter RAM S_RESET RQ SCLK SI RDY SO 11100000 00A5 A1 A0 D15 D0 11100000 00A5 A1 A0 D15 D0 Input of discontinuous address data into Hands-free parameter RAM [MS0296-E-00] 55 2005/03 [ASAHI KASEI] [AK7750] 2) Read during reset phase a) Control register data read (during reset phase) Control Register Read operations (at reset) are executed in 16-bit SCLK clocks. Control register values D7 ~ D1 are output at the falling edge of SCLK after command code is input. is invalid, ignore this bit. D0 Data transfer procedure Command code 70h, 72h, 74h, 76h, 78h, 7Ah, 7Ch, D8h, DAh, DCh note) 50h,54h,58h are not usable as they are dedicated for testing. For each bit function, please refer to section (2) Control Register Settings. S_RESET RQ SCLK SI SO 70h(example) D7 D1 74h(example) D7 D1 Reading of control register data [MS0296-E-00] 56 2005/03 [ASAHI KASEI] [AK7750] b) Program RAM read (during reset phase) Program RAM reads require inputting a command code and address to be accessed and setting SCLK to fall after setting SI to "H". The output data is synchronized with the falling edge of SCLK (Ignore RDY signal). When the requested read addresses are in consecutive locations, repeat the above procedure again by setting SI to "H". Data transfer procedure Command code input C1h ( 1 1 0 0 0 0 0 1 ) Read address input MSB ( 0 0 0 0 0 0 A9 A8) Read address input LSB (A7 . . . . . . A0) S_RESET RQ SCLK SI SO RDY 11000001 000000 A9A8 A7 A1 A0 D31 D0 D31 D0 CRAM Data Read [MS0296-E-00] 57 2005/03 [ASAHI KASEI] [AK7750] c) Coefficient RAM Read (during reset) Coefficient RAM reads require inputting a command code and address to be accessed and setting SCLK to fall after setting SI to "H". Data is output synchronized with the falling edge of SCLK. When the requested read addresses are in consecutive locations, repeat the above procedure again by setting SI to "H". Data transfer procedure Command code A1h Address upper Address lower (1 0 1 0 0 0 0 1 ) (0 0 0 0 0 0 A9 A8) (A7 . . . . . . A0) S_RESET RQ SCLK SI SO RDY 10100001 000000 A9A8 A7 A1 A0 D15 D0 D15 D0 CRAM data read [MS0296-E-00] 58 2005/03 [ASAHI KASEI] [AK7750] d) Offset RAM Data Read ( during reset ) It is possible to read out the stored Offset RAM data during reset. Read procedure involves inputting a command code and address to be accessed, and waiting for SCLK to fall after setting SI to "H". The data is then output in sync with the falling edge of SCLK. Data transfer procedure Command code Address 91h ( 1 0 0 1 0 0 0 1 ) ( 0 0 A5 . . . . A0) S_RESET RQ SCLK SI SO RDY 10010001 00 A5 A0 D12 D1 D0 D12 D1 D0 D12 D1 D0 OFRAM data read [MS0296-E-00] 59 2005/03 [ASAHI KASEI] [AK7750] e) Hands-Free Parameter RAM Read ( during reset ) Hands-Free program RAM reads require inputting a command code and address to be accessed and waiting for SCLK to fall after setting SI to "H". The data is then output synchronized with the falling edge of SCLK. When the requested read addresses are in consecutive locations, repeat the above procedure again by setting SI to "H". Read hands-free parameter RAM after writing "1" to HF_RST_N bit and HF bit in CONT5 register as shown in the page 71 Data transfer procedure Command code Address E1h ( 1 1 1 0 0 0 0 1 ) ( 0 0 A5 . . . . A0) S_RESET RQ SCLK SI SO RDY 11100000 00A5 A1 A0 D15 D0 D15 D0 D15 D0 Hands-Free Parameter RAM Read [MS0296-E-00] 60 2005/03 [ASAHI KASEI] [AK7750] 3) Writing During RUN a) Coefficient RAM write preparation and write ( under RUN condition ) This procedure is used to re-write the Coefficient RAM (CRAM) while a program is being executed. After inputting a command code, data for up to 16 consecutive addresses can be written. Next, input a write command code and a starting address. Rewriting of the RAM contents is executed whenever a re-written address is assigned. For example, this is how 5 writes are executed, starting at the Coefficient RAM address of " 10 ": Coefficient RAM execution address write execution location *) Note that address " 13 " is not processed until the data at address " 12 " is re-written. Data transfer procedure * Write preparation Command code A8h (1 0 1 0 1 0 0 0) Data (D15 D8) Data (D7 D0) * Write operation Command code A4h (1 0 1 0 0 1 0 0) Address upper (0 0 0 0 0 0 A9 A8) Address lower (A7 A0) Note) Be sure to follow the procedure of write preparation first, then write. An erroneous operation occurs if write is done without write preparation. "L" period of RDY for the write preparation is shorter than 1 master clock (20ns) under typical condition 7 8 9 10 11 13 16 11 12 13 14 15 S_RESET =H RQ SCLK SI 10101000 D15 D0 10100100 0 A9 A0 AL RDY Longer of (16-n) x 2 MCLK (n: number of data) and AL max 200ns RDYLG *) SO *) RDYLG pulse width is 2 LRCLK clock time maximum if a program is so written to rewrite a new address within a single sampling time. After this, RDY signal goes high. CRAM Write Preparation and Write [MS0296-E-00] 61 2005/03 [ASAHI KASEI] [AK7750] b) Offset RAM Write Preparation and Write ( under RUN condition ) This procedure is used to re-write Offset RAM (OFRAM) while a program is being executed. After inputting a command code, data at up to 16 consecutive addresses to be re-written can be input . Next, input a write command and a starting write address, and the re-write is executed whenever re-written address is assigned. For example, this is how 5 writes are executed, starting at the Offset RAM address of " 10 ": Offset RAM execution address write execution location Be noted that address " 13 " is not processed until data at address " 12 " is re-written. Data transfer procedure * Write preparation Command code 98h (1 0 0 1 1 0 0 0) Data (0 0 0 0 0 0 0 0) Data (0 0 0 D12 D8) Data (D12 D8) * Write operation Command code 94h (1 0 0 1 0 1 0 0) Address MSB (0 0 A5 A0) Note) Be sure to follow the procedure of write preparation first, then write. An erroneous operation occurs if write is done without write preparation. "L" period of RDY for the write preparation is shorter than 1 master clock (20ns) under typical condition 7 8 9 10 11 13 16 11 12 13 14 15 S_RESET =H RQ SCLK SI 10011000 00 D12 D0 10010100 00 A5 A0 AL RDY Longer of (16-n) x 2 MCLK (n: number of data) and AL max 200ns RDYLG *) SO *) RDYLG pulse width is 2 LRCLK clock time maximum if a program is so written to surely re-write a new address within a single sampling time. After this, RDY signal rises to high. ORAM Write Preparation and Write [MS0296-E-00] 62 2005/03 [ASAHI KASEI] [AK7750] c) External Conditional Jump Code Write ( under RUN condition ) External conditional jump code writes are executed in 2 bytes/set data. It is possible to input during in both reset and normal operation modes. Input data is set to each assigned register at the rising edge of LCRCK. RDY pin goes "L" after all data is transferred and it becomes "H" when the write operation is completed. External jump code is 8-bits and when any bit of this code and any single bit of "1" in the IFCON field matches, a jump instruction is executed. Write from microprocessor is inhibited until RDY becomes "H". Note) please be noted that phase of LRCLK is inverted in case of I2S compatible interface mode. Data transfer procedure Command code Code data S_RESET =H SCLK SI SO 11000100 D7 D0 C4h ( 1 1 0 0 0 1 0 0 ) (D7 D6 . . . . . A0) RQ LRCLK max: 2LRCLK RDY L ch R ch max: 0.25LRCLK External Conditional Jump Write Timing (during RUN) [MS0296-E-00] 63 2005/03 [ASAHI KASEI] [AK7750] 4) Read During RUNNING a) Control Register read out ( during RUN ) It is possible to read out Control Registers in RUN mode. D7 ~ D1 control register values are output at the falling edge of SCLK after a command code is input. As no register exists at D0 location, "0" is always output until the 16th rising edge of SCLK. Note) when D0 data is taken at the 16th rising edge of SCLK, it is not necessarily always "0", so please ignore the D0 value (as it is indeterminate after the 16th rising edge of SCLK). Data transfer procedure Command code 70h,72h,74h,76h,78h,7Ah,7Ch,D8h,DAh,DCh note ) 50h,54h,58h are not used as they are for testing. For each Bit function, please refer to section (2) Control Register Settings. S_RESET =H RQ SCLK SI SO 70h(example) D7 D1 74h(example) D7 D1 Example of Control Register Read [MS0296-E-00] 64 2005/03 [ASAHI KASEI] [AK7750] b) SO Read Out SO can output data that is on the DSP Data Bus (DBUS). Data is set using the @ MICR command and specifying a value in the DST field. When the data is set, DRDY becomes "H" and data is output in sync with the falling edge of SCLK. By setting SI to "H", DRDY becomes "L" and waits for the next instruction. Once DRDY becomes "H", the @ MICR instruction data that sets DRDY "H" is retained until SI is set to "H" or until 24 bits of data are output by SCLK clock (DRDY becomes "L" after outputting 24 data bits), and no further @MICR instruction is accepted. Output on SO pins is 24-bits long maximum. S_RESET =H RQ =H SI @MICR DRDY SCLK 24SCLK SO D D D DD DD 2 1 D 0 D 23 22 21 20 19 Data1 Data2 less than SCLK24 D DD D D DD 23 22 21 20 19 18 17 16 SO Read Out (during RUN) [MS0296-E-00] 65 2005/03 [ASAHI KASEI] [AK7750] 5 ) Simplified Write Error Check The AK7750 can easily check whether any error exists in the write data, using Cyclic Codes. (Note: the main purpose of this is to check erroneous writes due to induced noise etc. caused between microprocessor and DSP. As this is a CRC-based (cyclic redundancy check ) check, and as input data is checked before it is written into RAM and register, it does not guarantee 100 % write error detection ). Here definitions are made as follows : serial data D (x) : SI data being input during the time from RQ to fall to RQ to rise. Generator Polynomial G(x)=x16+x12+x5+1 (default value = 0) remainder R (x), when D(X) is divided by G (x) In order to perform a simplified write error check, perform the following: 1) Transfer serial data D(x) to be checked. 2) Write the remainder R(x) of serial data D(x) to register, using command code B6h. 3) Read out R(x) using command code D6h to check if it is correctly written (CRC check function operates even when no read is performed). 4) If the remainder of the serial data D(x) divided by G(x) is equal to R(x), SO outputs "H" at the rising edge of RQ until the following rising edge of RQ occurs for next serial data-write. When the SO output is used, as in the case of a read in RUN mode, there is a conflict. Therefore when a CRC check is done, do not execute read operation in RUN mode until the check is completed). If it is not equal to R(x), "L" is output. 5) If other serial data is to be checked, repeat 1 ) ~ 4 ) above. Details of Data Transfer Procedure 1) Write the register Writing remainder data R(x) is executed in 3 bytes/set data (24-bit). Data translate order. Command code B6h Upper 8bit of R(x) (D15 * * * * * * D8) Lower 8bit of R(x) ( D7 * * * * * * D0) 2) Read out the register Reading remainder data R(x) is executed in 3 bytes/set data (24-bit). Data translate order Command code D6h Upper 8bit of R(x) (D15 * * * * * * D8) Lower 8bit of R(x) ( D7 * * * * * * D0) R(x) RQ SCLK SI SO B6h D15 *** D D6h D15 *** D Example: Control register writing, reading [MS0296-E-00] 66 2005/03 [ASAHI KASEI] [AK7750] 3) CRC Check D(x) RQ SCLK SI SO The rest (D(x)/G(x))=R(x) 1010000 000000A9 A7***A1 A0 D15*** D0 B6h R(x) Rest of D(x)/G(x) The rest of D(x)/G(x)=R(x) CRC Check example. 4) Example of the R(x) made from D(x). Examples 1 2 3 D(X) D6ABCDh D2A5A5h A855557777AAAA0000FFFFh R(X) 1E51h 0C30h 2297h (8) ADC high-pass filter The AK7750 incorporates a digital high-pass filter (HPF) for canceling DC offset in the ADC. The HPF cut-off frequency is about 1 Hz (fs = 48 kHz). This cut-off frequency is proportional to the sampling frequency (fs). Cut-off frequency 48kHz 0.93Hz 44.1kHz 0.86Hz 32kHz 0.62Hz 8kHz 0.16Hz [MS0296-E-00] 67 2005/03 [ASAHI KASEI] [AK7750] (9) EEPROM Interface 1) Using the EEPROM interface Since the AK7750 has an integrate EEPROM interface, PRAM, CRAM, OFRAM and Control Register data can be loaded from the EEPROM after an initial RESET. Use AKM's 64Kbit/12Kbit serial EEPROM, the AK6512C/14C, when using the AK7750.. The data listed in section 2) Program Map, should be written into the EEPROM. The following operations are required when using the EEPROM. * Set EESEL pin to "H", (after reaching a proper oscillation when a crystal oscillator is used ) and set INIT_RESET pin to raise "H". Then internal counter starts to run which generates EEPROM control signals EECS , EESK and EESI, and EEPROM data is taken from EESO pin. * After taking all data, EESK and EESI become "L" and EECS to "H". EEST pin rises from "L" to "H", informing that loading has been completed. When EEST becomes "H", interface with microprocessor is enabled with EESEL pin as it stands at "H". When reading is required again, set INIT_RESET pin to "H" after executing initial reset ( INIT_RESET = "L") with EESEL kept at "H". Note that hands-free parameters can not be downloaded via EEPROM interface. [MS0296-E-00] 68 2005/03 [ASAHI KASEI] [AK7750] 2) Program map EEPROMADDRESS 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0BFEh 0BFFh 0C00h 0C01h 0C02h 0C03h 0C04h 0C05h 0C06h 0C07h 0C08h 1403h 1404h 1405h 1406h 1407h 1408h 1409h 140Ah 140Bh 1494h 1495h 1496h 1497h 1498h 1519A 151Ah 151Bh 151Ch 151Dh 151Eh 151Fh 1520h 1521h 1522h 1523h 1524h 1525h 1526h 1527h 1528h 1529h 152Ah DATA C0h 00h 00h PRAM0 DATA31-24 PRAM0 DATA23-16 PRAM0 DATA15-8 PRAM0 DATA7-0 PRAM1 DATA31-24 PRAM766 DATA7-0 PRAM767 DATA31-24 PRAM767 DATA23-16 PRAM767 DATA15-8 PRAM767 DATA7-0 A0h 00h 00h CRAM0 DATA15-8 CRAM0 DATA7-0 CRAM1 DATA15-8 CRAM1022 DATA7-0 CRAM1023 DATA15-8 CRAM1023 DATA7-0 90h 00h OFRAM0 DATA23-16 OFRAM0 DATA15-8 OFRAM0 DATA7-0 OFRAM1 DATA23-16 OFRAM46 DATA7-0 OFRAM47 DATA23-16 OFRAM47 DATA15-8 OFRAM47 DATA7-0 00h 60h DATA 62h DATA 64h DATA 66h DATA 68h DATA 6Ah DATA 6Ch DATA B6h CRC DATA15-8 CRC DATA7-0 Note PRAM WRITE command code PRAM address MSB side PRAM address LSB side PRAM address 0 MSB 8bit data PRAM address 0 MSB-1 8bit data PRAM address 0 MSB-2 8bit data PRAM address 0 LSB PRAM address 1 MSB PRAM address 766 LSB PRAM address 767 MSB 8bit data 8bit data 8bit data 8bit data PRAM address 767 MSB-1 8bit data PRAM address 767 MSB-2 8bit data PRAM address 767 LSB CRAM address MSB side CRAM address LSB side CRAM address 0 MSB CRAM address 0 LSB CRAM address 1 MSB 8bit data 8bit data 8bit data 8bit data CRAM WRITE command code CRAM address 1022 LSB 8bit data CRAM address 1023 MSB 8bit data CRAM address 1023 LSB 8bit data OFRAM WRITE command code OFRAM address OFRAM address 0 MSB OFRAM address 0 LSB OFRAM address 1 MSB OFRAM address 46 LSB OFRAM address 47 MSB 8bit data 8bit data 8bit data 8bit data 8bit data 8bit address OFRAM address 0 MSB-1 8bit data OFRAM address 47 MSB-1 8bit address OFRAM address 47 LSB Reserved CONT0 WRITE command code CONT0 data CONT1 WRITE command code CONT1 data CONT2 WRITE command code CONT2 data CONT3 WRITE command code CONT3 data CONT4 WRITE command code CONT4 data CONT5 WRITE command code CONT5 data CONT6 WRITE command code CONT6 data CRC WRITE command code CRC MSB 8bit data CRC LSB 8bit data [MS0296-E-00] 69 2005/03 [ASAHI KASEI] [AK7750] (10) DAC Soft Mute Operation DAC block in the AK7750 includes soft mute circuit. Soft mute operation is performed at digital domain. When the SMUTE bit goes to "1", the output signal is attenuated from 0dB level to - level during the LRCLK cycle time that is specified by SF1 bit and SF0 bit in CONT5 register plus additional 2LRCLK cycle time(max). When the SMUTE bit is returned to "0", the mute is cancelled and the output attenuation gradually changes to 0dB level by the same cycle. If the soft mute is cancelled before attenuating to - after starting the operation, the attenuation is discontinued and returned to 0dB by the same cycle. The soft mute is effective when S_RESET is "H" (DAC opeates normally) External mute circuit is recommended to suppress the pop noise at the reset. Attenuation value is initialized by INIT_RESET ="L", not S_RESET ="L" SMUTE bit setting value +2LRCLK(max) setting value +2LRCLK(max) 0dB Attenuation -dB GD GD Analog out Soft Mute Operation SMUTE bit setting value +2LRCLK(max) setting value +2LRCLK(max) 0dB Attenuation -dB S_RESET GD Analog out External Mute Circuit pop noise Mute ON Example of soft mute control@ S_RESET ="H" [MS0296-E-00] 70 2005/03 [ASAHI KASEI] [AK7750] (11) Hands-free mode The AK7750 has hands-free mode in addition to normal surround mode. The write "1" to HF_RST_N bit and HF bit in CONT5 register under system reset ( S _ RESET ="L") allows the AK7750 to hands-free operation mode. The AK7750 returns to surround mode by the execution of initial reset or the clear of HF_RESETN bit and HF bit. The AK7750 can change the attenuation level of noise canceller. If PID bit of CONT5 register is "0", the default attenuation level is used. If PID bit is "1", the attenuation level which is stored in the hands-free parameter RAM is used. Hands-free parameter must be downloaded to the address AFTER the AK7750 switches to hands-free mode. Please contact AKM for the detail of hands-free parameter contents. S _ RESET RQ SCLK SI 6Ah ECh E0h 00h DATA0 DAT A6 other DATA control register CONT5 Hands-free mode ON writing hands-free parameter RAM [MS0296-E-00] 71 2005/03 [ASAHI KASEI] [AK7750] 9. System Design (1) Connection example 0.1 10 0.1 0.1 0.1 0.1 0.1 Digital +3.3V 7 DVDD 22 21 20 SDIN1 SDIN2 SDIN3 11 DVDD 24 28 36 43 41 17 38 32 37 39 40 30 31 18 42 46 47 25 26 27 RESET CONTROL DVDD DVDD DVDD SMODE DRDY SO RDY RQ SI SCLK CS P I/F 19 SDIN4 Rd CL 33 XTO 34 CL XTI AK7750 HFST JX0 16 15 12 13 14 Analog Lch+ Analog LchAnalog Rch+ Analog Rch22K 1.5nF LRCLK_I BITCLK_I CLKO BITCLK_O LRCLK_O AINL+ AINLAINR+ AINRLFLT CKSX CKS1 CKS0 INIT_RESET CK_RESET S_RESET 64 63 62 61 49 SDOUT1 SDOUT2 SDOUT3 SDOUT4A 6 5 4 3 50 0.1 AOUTL AVDD AOUTR 54 53 55 Analog +3.3V 10 0.1 AVDD AVSS VREFL VCOM 51,52,60 59 58 10 0.1 56 0.1 AVDD 57 10 0.1 VREFH 8,10,23,29,35,44 DVSS BVSS 9,45 [MS0296-E-00] 72 2005/03 [ASAHI KASEI] [AK7750] (2) Periphery Circuit 1) Connection with EEPROM AK7750 INIT_RESET S_RESET RQ SCLK SI SO EESEL HFST /EEST L RDY DRDY RQ SCLK SI SO Micro cm p RDY/EESI DRDY/EECK CS /EESO LRCLK_O/ EECS 4-wire control CS AK7750 INIT_RESET S_RESET RQ SCLK SI SO EESEL HFST /EEST Micro cm p RQ SCLK SI SO H ST RDY DRDY EEPROM RDY/EESI DRDY/EECK CS /EESO LRCLK_O/ EECS 4-wire control + EEPROM SI CK SO CS AK7750 INIT_RESET S_RESET RQ SCLK SI SO EESEL H H H H HFST /EEST EEPROM RDY/EESI DRDY/EECK CS /EESO LRCLK_O/ EECS EEPRO M only SI CK SO CS [MS0296-E-00] 73 2005/03 [ASAHI KASEI] [AK7750] 2) Grounding and Power Supply When designing with the AK7750, AVDD and DVDD are separately decoupled in order to minimize digital noise. System Analog power supply is fed to AVDD. In general, power supply lines and ground lines are separately wired for the analog and digital portions, and they are connected together near the power supplies (terminals) on the printed circuit board. Small ceramic de-coupling capacitors should be connected as close as possible to the AK7750. 3) Reference Voltage An input voltage difference between VREFH pin and VREFL pin determines the analog full scale input and output. Normally, AVDD is connected to VREFH and AVSS to VREF. In order to eliminate high frequency noise, connect a 10 uF electrolytic capacitor and a 0.1 uF ceramic capacitor in parallel between VREFH and AVSS . The ceramic capacitor should be connected as close as possible to this pin. Digital signals, especially clocks should be wired as far as possible from the VREFH and VREFL pins in order to avoid coupling with the AK7750. The AK7750 common voltage is output on VCOM. Do not use this VCOM common voltage for connection with any external circuits. To eliminate high frequency noise, connect a 10-uF electrolytic capacitor and a 0.1 uF ceramic capacitor between VCOM and AVSS. These capacitors should be placed as close as possible to the VCOM pin. 4) Analog Input An analog signal is input to the internal modulator through differential input pins for each channel. The input voltage range is equal to difference in voltage between AIN+ and AIN- (VAIN = (AIN+) - (AIN-)), and equals FS = (VREFH - VREFL) x 0.4. When VREFH = 3.3 V and VREFL = 0.0 V, input range is 1.32 V. Output code format is in 2's complement. In the AK7750, the analog input is sampled at 3.072 MHz when fs = 48 KHz. A digital filter rejects noise ranging from 30 KHz to 3.042 MHz. Noise around the 3.072 MHz periphery band is not rejected. As no audio signals exhibit noise near 3.072 MHz, noise can be sufficiently attenuated using a simple RC filter. Analog input signal to the AK7750 must be biased as shown in Figure 1 Analog power supply voltage of the AK7750 is + 3.3 V (typ). Voltages higher than AVDD + 0.3 V & lower than AVSS - 0.3 V and current exceeding 10 mA should not be applied on the analog input pins (AINL+, AINL-, AINR+, AINR-). Injection of excessive current may destroy the internal protection circuits and may cause a latch-up that results in total device destruction. Therefore if 15 V power supplies are used in peripheral analog circuits, the analog input pins must be protected from signals exceeding absolute maximum ratings. [MS0296-E-00] 74 2005/03 [ASAHI KASEI] [AK7750] 10k Vop 10k 10k BIAS 1.32Vpp AVSS Signal 10k Vop 4.7k 4.7k + + NJM2100 330 1.5nF 330 BIAS AIN+ BIAS 10 + 0.1 AIN1.32Vpp AVSS Vop = VA+ = 3.3V AIN- Fig.1 Input Buffer Circuit Example ( Differential input ) 10k Vop BIAS AVSS 330 + 3.3nF Signal 10k Vop 4.7k 4.7k + NJM2100 AIN+ 10 BIAS 10 + 0.1 Vop = VA+ = 3.3V 330 BIAS AIN2.64Vpp AVSS AIN- Fig.2 Input Buffer Circuit Example ( Single-Ended input ) The AK7750 can also receive single-ended analog signals. In this case, the analog signal is fed to the AINinput pin (FS = (VREFH - VREFL) x 0.8= 2.64 Vp-p at VREFH = 3.3 V, VREFL = 0.0 V), and a bias voltage is fed to the AIN+ input pin. When 3.3 V OP amps are used in, low-saturation type OP amps are recommended. An electrolytic capacitor connected to AIN+ pin is effective in lowering secondary harmonics (refer to Figure 2). 5) Analog Output The analog output is single-ended. Output range is 2.00 Vp-p (typ) centered on VCOM. The Out-of-Band noise (shaping noise) generated by an internal delta-sigma modulator is attenuated by an on-chip switched capacitor filter (SCF) and a continuous time filter (CTF). Therefore it is not necessary to add an external filter for normal use. If ADC without anti-aliasing input filter is connected to DAC's output directly, the spurious noise may be appear. In this case, the insertion of low pass filter that has fo< 20kHz, 2nd order (>12dB/oct) is effective. The input code format is in 2's complement. Positive full-scale output corresponds to 7FFFFFh (@ 24 Bit) input code, Negative full scale is 800000h (@ 24 Bit) and VCOM voltage ideally is 000000h (@ 24 Bit). 6) Connection with Digital Circuit In order to minimize noise caused by Digital circuits, use low voltage logic ICs to connect the digital outputs. Recommended logic families are 74LV, 74LV-A, 74ALVC and 74AVC series ICs. [MS0296-E-00] 75 2005/03 [ASAHI KASEI] [AK7750] Package 64pin LQFP (Unit: mm) 12.00.3 10.0 48 49 33 32 Max 1.70 1.40 0.100.10 12.00.3 64 1 0.5 0.210.05 17 16 0.10 M 1.0 0.170.05 0~10 0.45 0.2 0.10 Material & Lead finish Package: Lead-frame: Lead-finish: Epoxy Copper Soldering plate (Pb free) [MS0296-E-00] 76 2005/03 [ASAHI KASEI] [AK7750] Marking XXXXXXX AK7750VT AKM 1 1) Pin #1 indication 2) ARM Logo 3) Date Code: XXXXXXX(7 digits) 4) Marking Code: AK7750VT 5) Asahi Kasei Logo IMPORTANT NOTICE These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd.(AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a): A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b): A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. [MS0296-E-00] 77 2005/03 |
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